Accelerated Photodynamic Cancer Therapy Planning with FullMonte - - PowerPoint PPT Presentation

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Accelerated Photodynamic Cancer Therapy Planning with FullMonte - - PowerPoint PPT Presentation

Feb 06, 2024 1.07k likes •1.24k views

Accelerated Photodynamic Cancer Therapy Planning with FullMonte Jeffrey Cassidy, PhD Candidate University of Toronto (Canada) #OpenPOWERSummit Photodynamic Therapy (PDT) for Cancer Photosensitizer Light Exposure (drug) (fluence J/cm 2 )

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Accelerated Photodynamic Cancer Therapy Planning with FullMonte Jeffrey Cassidy, PhD Candidate University of Toronto (Canada)

#OpenPOWERSummit

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Photodynamic Therapy (PDT) for Cancer

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Photosensitizer (drug) Light Exposure (fluence J/cm2) Tissue Oxygen Multiple FDA- approved drugs

  • Topical, IV, or oral

Normally present in tissue Surface illumination, Implanted fibre,

  • r intraoperative

Cells killed

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Photodynamic Therapy (PDT) for Cancer

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▪ Benefits ▪ Very low systemic toxicity ▪ Repeatable ▪ Highly targeted ▪ Simple, inexpensive delivery ▪ Single-shot, possibly outpatient basis

  • ▪ Challenges

▪ Variable outcomes ▪ Compute-intensive to model

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Photodynamic Therapy (PDT) for Cancer

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▪ Current use

▪ Skin (basal-cell carcinoma, actinic keratosis) ▪ Superficial oral cavity

  • ▪ Trials

▪ Prostate ▪ Bladder ▪ Head & neck ▪ Brain

  • Bladder model
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Image planning volume Delineate

  • rgans

Define dose parameters Propose plan Simulate Approve plan

PDT Treatment planning

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▪ Many sims required

▪ Many free parameters ▪ Properties variable

▪ Minutes per sim on CPU

  • Image courtesy Robert Weersink, Princess Margaret Cancer Centre
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PDT Treatment planning

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FullMonte simulation kernel

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Launch Draw step Region lookup Hop Interface Drop Exit Spin Dead

Monte Carlo simulation traces photons through tetrahedral mesh

“Digimouse” open-source mouse atlas (standard pre-clinical model)

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FullMonte simulation kernel

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  • ▪

Altera Stratix V FPGA

  • ▪

Flow stages <-> hardware modules

  • ▪

Queues at join points

  • ▪

1 step/clk @ 250 MHz

  • 


Launch Draw step Region lookup Hop Interface Drop Exit Spin Dead

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Preliminary Results

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Performance Metric FPGA* 1 instance (<25% area) 4 FPGA + server @ 4 inst/FPGA (projected)

Throughput / node 4x 64x Throughput / $capital 0.95x 3.6x Throughput / W 67x 41x

Intel Sandy Bridge (32nm) i7-2600K 3.6 GHz 4-core HT gcc –O3, multithreaded, hand-tuned SSE4 Price $1200 (excl. GPU & monitor)

  • Altera Stratix V (28nm) at Fmax=280MHz

Quartus II PowerPlay power estimation 4.5W single instance Price $5000 (Nallatech 385 list price)

  • *Prototype x86-hosted system, limited (48k) mesh size
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OpenPOWER/CAPI Scale-up

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CAPI platform:

  • ▪ Enables large meshes (no more 64k limit)

▪ On-chip cache for most frequently accessed ▪ Host serves long tail via CAPI

  • ▪ Maintains power & performance advantage
  • ▪ Provides support code (host & FPGA side)
  • ▪ Supports fast host-accelerator communication
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Digimouse (lung tumour)

Miss Rate

0.25 0.5 0.75 1

Cache Size (elements)

1 2 4 8 16 32 64 128 256 512 1k 2k 4k 8k 16k 32k 64k Static LRU Hybrid Oracle 1

OpenPOWER/CAPI Scale-up

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FPGA memory capacity

  • Misses served

by CAPI

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OpenPOWER/CAPI Scale-up

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64k

Digimouse (lung tumour)

Miss Rate (relative to Oracle=1.0)

1 2 3 4

Cache Size (elements)

1 2 4 8 16 32 64 128 256 512 1k 2k 4k 8k 16k 32k Static LRU Hybrid 2 3

Simple hybrid cache

  • ▪ L1 4-el. LRU

▪ L2 N-el. static

▪ Most frequent ▪ Banked ▪ Host-managed

  • 32% misses vs. pure LRU

and simpler to implement

  • +60% vs. clairvoyant

(perfect prediction)

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& BlueLink

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  • ▪ Designed with Bluespec SystemVerilog (BSV)

▪ Atomic rules for complex concurrency ▪ High performance ▪ Strong typing, good IP library, fast sim

  • ▪ Created open-source BSV library BlueLink

▪ Interface to IBM CAPI hardware & sim env. ▪ Simplified module interface ▪ IP for host <-> FPGA xfer to reg/MLAB/ BRAM ▪ Examples

  • github.com/jeffreycassidy/bluelink

(work in progress)

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Summary

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MC photon transport simulation on tetrahedral mesh

  • ▪ Performance per Watt -> FPGA

▪ Fixed-point (18b) arithmetic ▪ Spatial dataflow pipeline ▪ Inexpensive, effective custom caching

  • ▪

Tight host-FPGA coupling -> OpenPOWER CAPI ▪ Large meshes (>> FPGA on-chip mem.) ▪ Host mem. serves infrequent items ▪ Host-managed static cache set

  • >40x more performance/W vs CPU
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Acknowledgements

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PhD Supervisors

  • Prof. Vaughn Betz, Univ. Toronto ECE
  • Prof. Lothar Lilge, Princess Margaret Cancer Centre
  • Funding

IBM, Altera, CIHR, NSERC

  • In-Kind Support

IBM, SOSCIP , Altera, Bluespec

  • Discussion

Robert Weersink, PMCC Henry Wong, U Toronto