A Unified Program for Modifying Built-In Self-Test Architectures for - - PowerPoint PPT Presentation

▶
a unified program for modifying built in self test
SMART_READER_LITE
LIVE PREVIEW

A Unified Program for Modifying Built-In Self-Test Architectures for - - PowerPoint PPT Presentation

Oct 27, 2022 166 likes •529 views

A Unified Program for Modifying Built-In Self-Test Architectures for Xilinx Field Programmable Gate Arrays Neil Da Cunha Auburn University November 2 nd , 2011 Committee Members: Charles E. Stroud, Chair, Professor of Electrical and Computer

slide-1
SLIDE 1

A Unified Program for Modifying Built-In Self-Test Architectures for Xilinx Field Programmable Gate Arrays

Neil Da Cunha

Auburn University

November 2nd, 2011

Committee Members: Charles E. Stroud, Chair, Professor of Electrical and Computer Engineering Vishwani D. Agrawal, Professor of Electrical and Computer Engineering Victor P. Nelson, Professor of Electrical and Computer Engineering

slide-2
SLIDE 2

Abstract & Problem Statement

Abstract

A Built-In Self-Test (BIST) session for Xilinx Field Programmable Gate Arrays (FPGAs) is created with two programs. The first program, a BIST generation program, creates a template file which is then modified by the second program, a BIST modification program, into the different phases that make up a test session. Currently there are fifteenth BIST generation programs and fourteen BIST modification programs.

Problem Statement

To design a unified C program to modify any Field Programmable Gate Array (FPGA) Built-In Self Test (BIST) template file into the collection of different phases needed to properly test the full functionality of a desired component, also called a session.

slide-3
SLIDE 3

Overview of FPGAs

FPGAs are prefabricated integrated circuits that can implement the functionality of any digital circuit

◮ Configurable Logic Blocks

(CLBs)

slide-4
SLIDE 4

Overview of FPGAs

FPGAs are prefabricated integrated circuits that can implement the functionality of any digital circuit

◮ Configurable Logic Blocks

(CLBs)

◮ Programmable

Input/Output Buffers (IOBs)

slide-5
SLIDE 5

Overview of FPGAs

FPGAs are prefabricated integrated circuits that can implement the functionality of any digital circuit

◮ Configurable Logic Blocks

(CLBs)

◮ Programmable

Input/Output Buffers (IOBs)

◮ Programmable Interconnects

slide-6
SLIDE 6

Overview of FPGAs

FPGAs are prefabricated integrated circuits that can implement the functionality of any digital circuit

◮ Configurable Logic Blocks

(CLBs)

◮ Programmable

Input/Output Buffers (IOBs)

◮ Programmable Interconnects ◮ Configuration Memory

slide-7
SLIDE 7

Overview of FPGAs

FPGAs are prefabricated integrated circuits that can implement the functionality of any digital circuit

◮ Configurable Logic Blocks

(CLBs)

◮ Programmable

Input/Output Buffers (IOBs)

◮ Programmable Interconnects ◮ Configuration Memory ◮ Optional: Dedicated cores,

for example

◮ DSPs (Digital Signal

Processors)

◮ RAMs ◮ Power PC microprocessor

slide-8
SLIDE 8

Overview of BIST for FPGAs

Overview

◮ Basic idea: reprogram FPGA to test itself

◮ No area overhead or performance penalties ◮ Applicable to all levels of testing ◮ Application independent testing

slide-9
SLIDE 9

Overview of BIST for FPGAs

Overview

◮ Basic idea: reprogram FPGA to test itself

◮ No area overhead or performance penalties ◮ Applicable to all levels of testing ◮ Application independent testing

Challenges

◮ External memory to store BIST configuration data for the

BIST phases

◮ Goal: minimize number of phase as well as using compressed

configuration and partial reconfiguration techniques

◮ Test time = download + execute + results

◮ Dominated by download time ◮ Goal: minimize downloads and/or download time ◮ Results retrieval has the second most impact ◮ Goal: provide Pass/Fail indication (fault detection only) w/o

sacrificing diagnostic resolution (fault-tolerant apps)

slide-10
SLIDE 10

Overview of BIST for Xilinx FPGAs

Three major components

◮ Test Pattern Generators

(TPGs)

◮ Block Under Tests (BUTs)

◮ Multiple TPGs are used

to avoid fault escape

◮ Output Response Analyzers

(ORAs)

◮ Comparison based ◮ Latches “0” due to

mismatch

◮ Carry chain performs

iterative OR function

◮ Single pass/fail bit ◮ Read configuration

memory for diagnosis

slide-11
SLIDE 11

Table of BISTs developed for Xilinx FPGAs

BIST Types Devices Virtex-4 Virtex-5 Spartan6 CLB 10 6 In Progress LRAM 5 5

  • IOLOGIC

5 6

  • SERDES

9 10

  • DSP

5 11 In Progress BUFG 2 2

  • CRC
  • 2
  • BRAM

6 7 In Progress FIFO 5 4

  • ECC

2 3

  • FIFECC
  • 2
  • CASC
  • 2
slide-12
SLIDE 12

XDL - Xilinx Design Language

◮ A netlist format for describing and configuring circuits at the

component level

◮ Used to carefully place and configure the BIST circuitry ◮ Meant for internal work at Xilinx, as a result there is no

formal documentation

◮ Everything had to be learned by experience or experimentation

BAD Syntax

i n s t ”name” ” type ” , placed loc , cfg ” lorem ipsum delorem ” ;

GOOD Syntax

i n s t ”name” ” type ” , placed loc , cfg ” lorem ipsum delorem ” ;

slide-13
SLIDE 13

FPGA BIST Flow

For a particular device and BIST type

  • 1. A BIST generation program

creates a generic, unrouted template in xdl for a particular device and BIST type

i n s t ”name” ” type ” , placed loc , cfg ” Lorem ipsum d o l o r s i t ” ; net ”name” ,

  • utpin

”comp name” pin , i n p i n ”comp name” pin , i n p i n ”comp name” pin , ;

slide-14
SLIDE 14

FPGA BIST Flow

For a particular device and BIST type

  • 1. A BIST generation program

creates a generic, unrouted template in xdl for a particular device and BIST type

  • 2. The xdl file is converted to an

ncd file by the Xilinx xdl program

slide-15
SLIDE 15

FPGA BIST Flow

For a particular device and BIST type

  • 1. A BIST generation program

creates a generic, unrouted template in xdl for a particular device and BIST type

  • 2. The xdl file is converted to an

ncd file by the Xilinx xdl program

  • 3. The ncd file is then routed in

Xilinx FPGA Editor or using Xilinx par program

slide-16
SLIDE 16

FPGA BIST Flow

For a particular device and BIST type

  • 1. A BIST generation program

creates a generic, unrouted template in xdl for a particular device and BIST type

  • 2. The xdl file is converted to an

ncd file by the Xilinx xdl program

  • 3. The ncd file is then routed in

Xilinx FPGA Editor or using Xilinx par program

  • 4. The routed ncd file is converted

back into an xdl file using Xilinx xdl program

i n s t ”name” ” type ” , placed loc , cfg ” Lorem ipsum d o l o r s i t ” ; net ”name” ,

  • utpin

”comp name” pin , i n p i n ”comp name” pin , i n p i n ”comp name” pin , pip ”name” ”name” − > ”name” , pip ”name” ”name” − > ”name” , ;

slide-17
SLIDE 17

FPGA BIST Flow

For a particular device and BIST type

  • 1. A BIST generation program

creates a generic, unrouted template in xdl for a particular device and BIST type

  • 2. The xdl file is converted to an

ncd file by the Xilinx xdl program

  • 3. The ncd file is then routed in

Xilinx FPGA Editor or using Xilinx par program

  • 4. The routed ncd file is converted

back into an xdl file using Xilinx xdl program

  • 5. This routed XDL file is then

configured into the necessary phase for a BIST type by a BIST modification program

i n s t ”name” ” type ” , placed loc , cfg ” Ut enim ad minim ” ; net ”name” ,

  • utpin

”comp name” pin , i n p i n ”comp name” pin , i n p i n ”comp name” pin , pip ”name” ”name” − > ”name” , pip ”name” ”name” − > ”name” , ;

slide-18
SLIDE 18

FPGA BIST Flow

For a particular device and BIST type

  • 1. A BIST generation program

creates a generic, unrouted template in xdl for a particular device and BIST type

  • 2. The xdl file is converted to an

ncd file by the Xilinx xdl program

  • 3. The ncd file is then routed in

Xilinx FPGA Editor or using Xilinx par program

  • 4. The routed ncd file is converted

back into an xdl file using Xilinx xdl program

  • 5. This routed XDL file is then

configured into the necessary phase for a BIST type by a BIST modification program

  • 6. Optionally converted to an ncd or

a bit file

i n s t ”name” ” type ” , placed loc , cfg ” Ut enim ad minim ” ; net ”name” ,

  • utpin

”comp name” pin , i n p i n ”comp name” pin , i n p i n ”comp name” pin , pip ”name” ”name” − > ”name” , pip ”name” ”name” − > ”name” , ;

slide-19
SLIDE 19

BIST Programs in detail

BIST generation programs

◮ Generate the initial BIST

template

◮ Specifies the location and

interconnections of all BIST components

◮ One for every device and

BIST type

◮ Share very little code in

common BIST modification programs

◮ Configures template into

various phases

◮ Specifies configuration of

BIST components

◮ One for every device and

BIST type except for BUFG BIST

◮ Share code and functionality

with each other

slide-20
SLIDE 20

Problem Statement Restated

Problem Statement

“To design a unified C program to modify any Field Programmable Gate Array (FPGA) Built-In Self Test (BIST) template file into the collection of different phases needed to properly test the full functionality of a desired component, also called a session.”

Additional Requirements

The program must meet the following criteria, in order of importance:

  • 1. Has to describe an identical architecture/circuit
  • 2. Has to be easily extendible
  • 3. Reuse code whenever possible
  • 4. Produce consistently formatted xdl files
slide-21
SLIDE 21

Overview of the Program

Three main sections to the program

  • 1. Input validation
  • 2. XDL Processing Finite State Machine

◮ Reconfigure components - mainly BUTs ◮ Inverting clocks ◮ Removing nets for certain forms of BIST

  • 3. Post-Processing - optionally outputting an ncd or bit file
slide-22
SLIDE 22

XDL Processing Finite State Machine

◮ parse initalized to COPY

state

slide-23
SLIDE 23

XDL Processing Finite State Machine

◮ parse initalized to COPY

state

◮ COPY state checks for

keywords and sets parse

slide-24
SLIDE 24

XDL Processing Finite State Machine

◮ parse initalized to COPY

state

◮ COPY state checks for

keywords and sets parse

◮ INST state searches for

components depending on BIST type

slide-25
SLIDE 25

XDL Processing Finite State Machine

◮ parse initalized to COPY

state

◮ COPY state checks for

keywords and sets parse

◮ INST state searches for

components depending on BIST type

◮ CFG state writes

appropriate configuration for phase, type and device

slide-26
SLIDE 26

XDL Processing Finite State Machine

◮ parse initalized to COPY

state

◮ COPY state checks for

keywords and sets parse

◮ INST state searches for

components depending on BIST type

◮ CFG state writes

appropriate configuration for phase, type and device

◮ Custom states are just the

CFG state for one BIST type and device

slide-27
SLIDE 27

Test Case for Extensibility: Spartan6

◮ BIST for Spartan6 was developed after V45mod was complete ◮ Three versions developed - DSP, CLB, and RAM BIST ◮ Simply a matter of making some minor changes which I will

  • utline in the next slide
slide-28
SLIDE 28

Examples of modified code

Adding Spartan6 to the list of valid devices

1 typedef enum 2 { 3

V4 , V5 , S6

4 }

f p g a S e r i e s ;

slide-29
SLIDE 29

Examples of modified code

Making sure Spartan6 is recognized as a valid device

6 //

Checks which d e v i c e we are d e a l i n g with

7

i f ( strcmp ( argv [ 3 ] , ”V4” ) == 0 | | strcmp ( argv [ 3 ] , ”v4” ) == ֒ → 0)

8 { 9

d e v i c e = V4 ;

10 } 11 e l s e

i f ( strcmp ( argv [ 3 ] , ”V5” ) == 0 | | strcmp ( argv [ 3 ] , ”v5” ) ֒ → == 0)

12 { 13

d e v i c e = V5 ;

14 } 15 e l s e

i f ( strcmp ( argv [ 3 ] , ”S6” ) == 0 | | strcmp ( argv [ 3 ] , ” s6 ” ) ֒ → == 0)

16 { 17

d e v i c e = S6 ;

18 } 19 e l s e 20 { 21

p r i n t f ( ” E r r o r : I n v a l i d

  • r

non−supported d e v i c e . Run the ֒ → program with no arguments \n” ) ;

22

return 3;

23 }

slide-30
SLIDE 30

Examples of modified code

Adding Spartan6 Configuration Data

25 e l s e i f ( d e v i c e == S6 && type == CLB) 26 { 27 switch ( phase ) 28 { 29 case 1: 30 f p r i n t f ( fpo , ”A5LUT::#LUT: O5=A1@A2@A3@A4@A5 A6LUT::#LUT: O6= ֒ → A1@A2@A3@A4@A5@A6 AFF::#FF AFFSRINIT : : SRINIT1 AFFMUX : : O6 AOUTMUX ֒ → : : A5Q A5FFSRINIT : : SRINIT0\n” ) ; 31 f p r i n t f ( fpo , ”B5LUT::#LUT: O5=˜(A1@A2@A3@A4@A5) B6LUT::#LUT: O6=˜( ֒ → A1@A2@A3@A4@A5@A6) BFF::#FF BFFSRINIT : : SRINIT1 BFFMUX : : O6 BOUTMUX: : ֒ → B5Q B5FFSRINIT : : SRINIT0\n” ) ; 32 f p r i n t f ( fpo , ”C5LUT::#LUT: O5=A1@A2@A3@A4@A5 C6LUT::#LUT: O6= ֒ → A1@A2@A3@A4@A5@A6 CFF::#FF CFFSRINIT : : SRINIT1 CFFMUX : : O6 COUTMUX ֒ → : : C5Q C5FFSRINIT : : SRINIT0\n” ) ; 33 f p r i n t f ( fpo , ”D5LUT::#LUT: O5=˜(A1@A2@A3@A4@A5) D6LUT::#LUT: O6=˜( ֒ → A1@A2@A3@A4@A5@A6) DFF::#FF DFFSRINIT : : SRINIT1 DFFMUX : : O6 DOUTMUX: : ֒ → D5Q D5FFSRINIT : : SRINIT0\n” ) ; 34 f p r i n t f ( fpo , ”CEUSED::#OFF CLKINV : : CLK B SRUSED::#OFF SYNC ATTR : : SYNC” ) ; 35 break ;

slide-31
SLIDE 31

Error Codes

◮ Error codes were added to the program to diagnose abnormal

behaviour

Error Code Meaning Normal Operation, no errors reported. 1 Too few arguments. 2 Too many arguments. 3 Invalid or non-supported device. Currently supported devices are the Virtex-4, Virtex-5, and Spartan-6. 4 Invalid BIST type or the specified device does not support the selected BIST type. 5 Virtex-4 Block RAMs do not have a FIFECC mode, and therefore there is no FIFECC BIST available for the Virtex-4. 6 Virtex-4 does not have a CRC component, therefore there is no CRC BIST available for the Virtex-4 7 Invalid phase argument for desired BIST type and device. 8 Invalid optional argument. Valid optional arguments are either “ncd”

  • r “bit” in either all uppercase or lowercase. Mixed case is not currently

supported. 9 The input file is not valid or can not be read. 99 This refers to an error that should have been caught earlier by previous error checking measures.

Table: Error Codes and Meanings

slide-32
SLIDE 32

Verification

◮ One of the goals was to create a standardized format for the

  • utput XDL files

◮ Previous BIST modification program did not have a unified

standard

◮ Problem is that new xdl files don’t match the old XDL files

◮ Files can not be compared directly

◮ Solution was to use the xdl internal parser

◮ Convert both files to ncd format, and then back to xdl ◮ If the two xdl files don’t match exactly, the difference would be

an error in my program

slide-33
SLIDE 33

Goals Status

  • 1. Has to describe an identical architecture/circuit
  • 2. Be easily extendible
  • 3. Reuse code whenever possible
  • 4. Produce consistently formatted XDL files
slide-34
SLIDE 34

Other Projects and Publications

Projects

◮ Mixed-Signal BIST for Analog Circuits ◮ Programmable Clock Buffer BIST for Virtex-4 and Virtex-5 FPGAs ◮ Designed an FPGA Logic Analyzer Circuit for testing Analog to Digital

Converters (ADCs)

◮ Rewriting the IBM CMOS 8RF cell library in AUSIM for fault testing in

AUSIM

Publications

◮ C. Stroud and N. Da Cunha, Built-In Self-Test of Programmable Clock

Buffers in Virtex-4, Virtex-5 and Virtex-6 FPGAs, Proc. IEEE Southeast

  • Symp. on System Theory, pp. 228-232, 2011

◮ James M. Tacey, Michael A. Lusco, Neil S. Da Cunha, Jie Qin,

”Weighted Bridging Fault Coverage Using Capacitance Extraction”, Proc. IEEE Southeastern Symp. on System Theory, 2011