A Sum Error Detection Scheme for Decimal Arithmetic www.itmati.com - - PowerPoint PPT Presentation

A Sum Error Detection Scheme for Decimal Arithmetic

www.itmati.com

Alvaro Vázquez

• ITMATI. Technological Institute for Industrial Mathematics (Spain)

and Elisardo Antelo University of Santiago de Compostela (Spain)

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

Summary

1 Introduction 2 BCD sum checker 3 Mixed binary/BCD sum checker 4 Sign-magnitude sum checker 5 Evaluation and Comparison 6 Conclusion

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

Summary

1 Introduction 2 BCD sum checker 3 Mixed binary/BCD sum checker 4 Sign-magnitude sum checker 5 Evaluation and Comparison 6 Conclusion

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

Objectives of this work

Concurrent error detection for both binary and BCD addition/subtraction. Fully protection against single faults or event upsets (soft errors). Avoid hardware duplication. Avoid adder redesign.

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

Sum checkers for concurrent error detection

• 1. Self-checking adders.

⊲ Require adder redesign. ⊲ Based on a variety of techniques:

• Parity prediction.
• Residue codes.
• Berger code prediction.
• Double-rail checking of carries.
• 2. Separable:

⊲ Avoid adder redesign. ⊲ Only two different proposal:

• Unit duplication (sheer redundancy).
• Carry-save checkers.

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

Unit duplication

X Y err S Main Adder Z

Replicated Adder

Error Checker

(a) General layout.

s 0 z s n−1 z n−1 s k−1 z k−1 s k z k

err

OR TREE

(b) Error checker (comparator). Figure: Sum checking using unit replication.

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

Carry-save checkers for binary addition (I)

Previous work: Separable carry-free error detection mechanisms for fast, unpipelined binary integer/fixed-point addition:

⊲ Used to check A + B = K without carry propagation (Cortadella et al,

1992).

⊲ Lazy adder checker: carry-save checker with custom full-adder

(Yilmaz et al, 2007).

⊲ Long residue checker: carry-save checker with standard cell

full-adders (Sullivan et al, 2012).

Separable error detectors for pipelined mixed parallel prefix and carry-ripple adders (Sullivan et al, 2013).

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

Carry-save checkers for binary addition (II)

X Y Adder err

Carry−free Adder SV CV

S Error Checker

Figure: General block diagram.

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

Carry-save checkers for binary addition (III)

Mux−2 1

k

x

k

y

k

s

k

sv cv

k−1 k

cv

(a) Lazy Adder Checker

k

s

k

x

k

y

k

sv cv

k−1 k

cv

Full Adder

(b) Long Residue Checker

svk

=

pk ⊕ sk = pk ⊕ pk ⊕ ck = ck cvk

=

pk yk ∨ pk sk = pk yk ∨ pk sk = ck+1 svk

=

xk ⊕ yk ⊕ sk = pk ⊕ pk ⊕ ck = ck cvk

=

xk yk ∨ (xk ∨ yk) sk = xk yk ∨ pk ck = ck+1

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

New contributions of this work

Algorithm and architecture of separable carry-save (CS) checker for the following operations/number systems:

• 1. 10’s complement BCD add/sub.
• 2. Mixed 2’s complement binary/10’s complement add/sub
• 3. BCD sign-magnitude add/sub ⇒ Extension to mixed binary/BCD SM

straightforward

Simple conditions for error detection in terms of word-length

• perands X, Y and S ⇒ Fused into single condition by recoding to

radix-16. Decimal CS addition implemented using binary radix-16 + simple combinational logic for decimal correction ⇒ Easy integration into the binary CS checker.

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

Summary

1 Introduction 2 BCD sum checker 3 Mixed binary/BCD sum checker 4 Sign-magnitude sum checker 5 Evaluation and Comparison 6 Conclusion

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

Word-length operand condition for add/sub checking (I)

Binary 2’s complement

• 1. Addition:

X + Y = S

⇒

X + Y − S = 0

⇒

X + Y + S + 1 = 2n − 1

• 2. Subtraction:

X − Y = S

⇒

X − Y − S = 0

⇒

X + Y + S + 1 = 2n − 1

• 3. Add/Sub:

X + YB + S+ sub =

n−1

∑

k=0

2k =

n/4−1

∑

i=0

(15) 16i ⇔

n

k=0(svk ⊕ hvk) = 0

YB =

• Y

IF(sub == 0) Y ELSE

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

Word-length operand condition for add/sub checking (II)

BCD 10’s complement

• 1. Addition:

X + Y = S

⇒

X + Y − S = 0 ⇒ X + Y + S =

p−1

∑

i=0

(15) 10i

with −S = S − ∑

p−1 i=0 (15) 10i.

• 2. Subtraction:

X − Y = S ⇒ X − Y − S = 0 ⇒

⇒ X + Y + S −

p−1

∑

i=0

(15) 10i =

p−1

∑

i=0

(15) 10i

• 3. Add/Sub:

X + YD + S + sub ?

=

p−1

∑

i=0

(15) 10i

YD =

• Y

IF(sub == 0) Y + 6 ELSE

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

Binary radix-16 approximation of BCD Carry-save (I) |Xi + YD

i + Si + Ci|10

?

= 15 ⇒ |Xi + YB

i + SB i + Ci|16

?

= 15

Ci+1 = Gi ∨ AiCi Gi =

• 1

IF(Xi + YA

i ≥ 16)

ELSE Ai =

• 1

IF(Xi + YA

i ≥ 15)

ELSE YA

i = YD i + 6

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

Proposed architecture for BCD add/sub checking

Y B

CV

err

SV HV

Error Checker 1−bit left shift 3:2 Carry−save adder

Conditional bit inversion

sub B S I

Digitwise decimal corrections

X Y S

(c) General layout.

Y i X i i Y A i Y B i G i I Digitwise +6 if sub=0 Bit inversion if sub=1 4 4 4 4 (4 bits) i A Carry−prefix tree Digitwise −6 if Ai=0 sub

(d) Decimal correction block.

I

i

s

i,0

s

i,2

s

i,3

s

i,1

s

i,3

s

i,2

s

i,1

s

i,0

B B B B

(e) Sum inversion block.

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

Binary radix-16 approximation of BCD Carry-save (II)

YA

i =

• Yi − 6

IF(sub == 0) Yi ELSE YB

i =

• YA

i − 6

IF(Ai == 0) YA

i

ELSE SB

i =

• Si − 6

IF(Ii == 1, Si == 9) Si ELSE Ii = AiGi

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

Fault secure checker

There might be a case that an induced error in Si could be not detected when Ii = AiGi == 1 ⇔ Xi + YD

i == 9

by using S∗

i = Xi + YD i + C∗ i

Only two possible values of Si could not be detected as errors when Ii == 1: Si = 0 when C∗

i == 1 Si = 9 when C∗ i == 0. But we

discard Si = 0 by construction. It could be possible that when Ii == 1, still an error of 9 is not detected due to an error in C∗

i

Such an error would be detected always in the least significant bit, since C0 = sub is a preasigned value.

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

Summary

1 Introduction 2 BCD sum checker 3 Mixed binary/BCD sum checker 4 Sign-magnitude sum checker 5 Evaluation and Comparison 6 Conclusion

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

Architecture Mixed Bin/BCD Checker

X i i Y A i Y B 4 4 Y i Bit inversion if sub=1 sub 4 (4 bits) 4 Digitwise +6 if sub=0 and dec=1 dec and dec=1 Digitwise −6 if Ai=0 A Carry−prefix computation dec dec i i I G i

Figure: Decimal correction block for the bin/dec sum error checker.

YB

i = YA i − 6 · (Ai dec)

YA

i =

  

Yi IF(sub == 0, dec == 0) Yi ELSEIF(sub == 1) Yi + 6 ELSE

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

Summary

1 Introduction 2 BCD sum checker 3 Mixed binary/BCD sum checker 4 Sign-magnitude sum checker 5 Evaluation and Comparison 6 Conclusion

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

Sign-magnitude addition

Input operands: FX = (−1)sX X , FY = (−1)sY Y FS

=

X + (−1)sub Y = (−1)sX X + (−1)sY+sub−sX Y

• =

(−1)sign(S) S

with sub = 0 for addition sub = 1 for subtraction. Magnitude addition: S = |X + (−1)eop Y| Sign: sign(S) = sX eop ∨ sign(X − Y) eop sign(X − Y) =

• IF(X ≥ Y)

1 ELSE

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

Sum paths and conditions to check

S =

  

X + Y IF(eop == 0) X − Y IF(eop == 1, sign(X − Y) == 0)

−(X − Y)

IF(eop == 1, sign(X − Y) == 1) First path (eop = 0): X + Y + S =

p−1

∑

i=0

(15) 10i

For the second path (eop = 1, sign(X − Y) == 0): X + Y + 6 + S + 1 =

p−1

∑

i=0

(15) 10i

For the third path (eop = 1, sign(X − Y) == 0): S + X − Y = 0 ⇒ X + Y + S =

p−1

∑

i=0

(15) 10i

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

Replacement of Decimal by Binary (Radix-16) checking |Xi + YD

i + SD i + Ci|10

?

= 15 ⇒ |XB

i + YB i + SB i + Ci|16

?

= 15

YD

i

=   

Yi IF(eop == 0) Yi + 6 IF(eop == 1, sign(X − Y) == 0) Yi IF(inc == 1) SD

i

=

Si (inc) ∨ Si inc with inc = eop sign(X − Y).

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

Correction of radix-16 approximation for 3rd path

1) YD (decimal) replaced by YB (binary). 2) Correction of Xi digits for the 3rd path when Ci+1 is one: XB

i =

• Xi + 6

IF(Gi == 1, inc == 1) Xi ELSE 3) Correction of Si due to Ci+1 ≈ Gi when inc = 1: SB

i =

• Si + 6

IF(Ii == 1, Si == 9) Si ELSE with Ii = dec AiGi.

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

Architecture

X i i Y A Y i i Y B 4 Digitwise −6 if Ai=0 and inc=0 4 (4 bits) 4 Carry−prefix computation i I G i Digitwise +6 if eop=0 Bit inversion if eop=1 eop 4 4 Digitwise +6 if Gi=1 and inc=1 A i inc i X B 4

(a) Decimal correction block (1 digit slice).

Carry−prefix tree G i A i 2 G 2 A p−1 A G p−1 2 eop

• ut

C inc eop

(b) inc = eop sign(X − Y).

s

i,0

s

i,2

s

i,1

s

i,0

B s

i,2

s

i,1

B B I

i

s

i,3

B s

i,3

inc

(c) Sum inversion.

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

Summary

1 Introduction 2 BCD sum checker 3 Mixed binary/BCD sum checker 4 Sign-magnitude sum checker 5 Evaluation and Comparison 6 Conclusion

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

True-complement adders

Fast Adder Type of sum checker Proposed Fast 2nd Adder+Error checker Slow 2nd Adder+Error checker Delay/Area Delay Area Delay Area Area (#FO4/Nand2) (tfo4/ratio) (Nand2/ratio) (tfo4/ratio) (Nand2/ratio) (Nand2/ratio) 64-bit/16-BCD digit architectures Binary 13.9/1640 8.0/0.65 895/0.60 5.4/0.40 1870/1.20 1670/1.00 Decimal 15.9/2220 8.9/0.80 1230/0.55 5.4/0.35 2450/1.15 2250/1.00 Mixed 16.1/2450 8.9/0.80 1380/0.55 5.4/0.35 2680/1.10 2400/1.00 136-bit/34-BCD digit architectures Binary 16.1/3800 8.8/0.60 1965/0.55 6.2/0.40 4285/1.15 3850/1.00 Decimal 18.1/4920 9.7/0.55 2685/0.60 6.2/0.35 5405/1.10 5100/1.05 Mixed 18.3/5370 9.7/0.60 2885/0.55 6.2/0.35 5855/1.10 5450/1.00

Table: Comparison results for unpipelined sum checkers (true-complement addition).

Note: Assuming a cycle time of 13 FO4 delays, carry-save checkers can be placed in a single cycle stage after the adder in a pipelined design.

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

BCD Sign-magnitude adders

Architecture Delay Area (#FO4/ratio) (Nand2/ratio) 16-BCD digit architectures Proposed checker 10.9/0.55 1680/0.55 Sign-mag. BCD adder 19.2/1.00 3200/1.00 2nd Add + Error checker 5.4/0.30 3430/1.10 34-BCD digit architectures Proposed checker 11.7/0.55 3585/0.55 Sign-mag. BCD adder 22.1/1.00 7010/1.00 2nd Add + Error checker 6.2/0.30 7495/1.10 Table: Comparison results for unpipelined sign-magnitude BCD sum checkers.

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

Summary

1 Introduction 2 BCD sum checker 3 Mixed binary/BCD sum checker 4 Sign-magnitude sum checker 5 Evaluation and Comparison 6 Conclusion

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

Conclusion

Separable carry-save checkers for error detection of

• 1. 10’s complement addition/subtraction.
• 2. Mixed 2’s complement/10’s complement addition/subtraction.
• 3. Sign-magnitude BCD addition/subtraction.

Decimal carry-save implemented with binary carry-save adders plus simple correction logic. Adder redesign not required, simplifying pipelining and hardware reuse. Similar performance as unit duplication+comparison checker with roughly half the area. TODO: Extension of SM adder checker to FP binary128/decimal128 significand add/sub by adding rounding support.

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

Acknowledgment

This work was Supported by Projects IN2016-76373-P (AEI/FEDER, UE) and TIN2013-41129-P, and Networks R2016/045 and R2016/037. This work was also Supported by Xunta de Galicia, ITMATI and Repsol through the Joint Research Unit IN853A 2014/03.

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Introduction BCD sum checker Mixed binary/BCD sum checker Sign-magnitude sum checker Evaluation and Comparison Conclusion

Thank you. Questions?

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