A RISC-V SystemC-TLM simulator CARRV 2020 Mrius Montn Outline - - PowerPoint PPT Presentation

A RISC-V SystemC-TLM simulator

CARRV 2020 Màrius Montón

Outline

• Introduction
• Simulator
• Tests
• Conclusions

Motivation

Motivation

Develop a simple simulator based on a RISC-V CPU

• As a embedded processor

○ Small CPU ○ Simple memory scheme

• Using a simple toolchain

○ Out-of-the-box binary from gcc ○ Easy tools ○ No semi-hosting facilities

• And easy expandable

○ Attach new peripherals ○ Add new RISC-V extensions ○ Modify CPU architecture

Simulator

SystemC as language

• C++ based, well known language
• Add-ons HW to C++
• Simulation based
• Possibility to synthesis with external tools

TLM-2 as modeling

• Transaction based
• Common interface

Simulator

TLM Transactions & sockets

• Communication channel
• Abstraction of a bus

○ Details not important ○ Information about time and address/data

• Increase simulation speed
• Sockets encapsulates all this

○ Initiator/Target <--> Master/Slave ○ Interchangeable

Simulator

Simulator

Instruction set simulator

• Execute and decode

○ Extensions

• Register file

○ x0-x31 ○ PC ○ CSR

• Harvard

○ Data / Instr. Bus

• IRQ port

Simulator

Bus controller

• Data / Instr. Input sockets
• Out sockets

○ To memory ○ Peripherals ■ Trace ■ Timer ■ …

• Memory map

Simulator

Peripherals

• Memory

○ Exe file pre-loaded

• Trace for

debug/console

• Timer, trigger IRQ

Simulator

Simulation helper

• Log execution

○ Log file ○ Operands and result

• Performance metrics

○ Memory accesses ○ Registers accesses ○ Instructions executed

Simulator

Simulation helper

• Log execution

○ Log file ○ Operands and result

• Performance metrics

○ Memory accesses ○ Registers accesses ○ Instructions executed

Simulator

Simulation helper

• Log execution

○ Log file ○ Operands and result

• Performance metrics

○ Memory accesses ○ Registers accesses ○ Instructions executed

Pure bare-metal simulator

• ECALL, EBREAK → implemented to help debugger, not calling OS

○ ECALL Stops simulation ○ EBREAK Raise Breakpoint exception

• Need to implement _write() _read() functions in sim code
• Support full C std libraries for sim code
• FreeRTOS porting

Docker version

• Not need to compile anything, just hit & run
• Performance penalty

Simulator

Pure bare-metal simulator

• ECALL, EBREAK → implemented to help debugger, not calling OS

○ ECALL Stops simulation ○ EBREAK Raise Breakpoint exception

• Need to implement _write() _read() functions in sim code
• Support full C std libraries for sim code
• FreeRTOS porting

Docker version

• Not need to compile anything, just hit & run
• Performance penalty

Simulator

Pure bare-metal simulator

• ECALL, EBREAK → implemented to help debugger, not calling OS

○ ECALL Stops simulation ○ EBREAK Raise Breakpoint exception

• Need to implement _write() _read() functions in sim code
• Support full C std libraries for sim code
• FreeRTOS porting

Docker version

• Not need to compile anything, just hit & run
• Performance penalty

Simulator

Tool-chain

• Used gcc for RISC-V
• Only small CFLAGS required

CFLAGS = -Wall -I. -O0 -static -march=rv32imac -mabi=ilp32

• -specs=nosys.specs
• Default linker script
• Uses HEX file from elf output

> objcopy -Oihex file.elf file.hex

Simulator

Tests

Check ISS correctness - Compliance tests

• riscv/riscv-tests passed
• riscv-compliance test passed

Check whole simulator - C programs

• Simple C programs, using libraries
• FreeRTOS porting
• Dhrystone

Tests

Tests

• Consistent
• Penalty using trace
• Penalty using Log

Conclusions

Simulator is working fine

• Complex programs running OK
• No cross-tools modifications
• Easy to use and understand

Need to add more components

• Add I/O peripherals
• Add FLASH memory for instr.
• Model a real MCU

Conclusions

Increase performance, but similar to other SystemC simulators Open-Source https://github.com/mariusmm/RISC-V-TLM

Conclusions