A Novel Modular Adder for One Thousand Bits and More Using Fast - - PowerPoint PPT Presentation

¡ A Novel Modular Adder for One Thousand Bits and More Using Fast Carry Chains of Modern FPGAs

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Marcin Rogawski, Ekawat Homsirikamol & Kris Gaj George Mason University USA

Co-Authors

Ekawat Homsirikamol a.k.a “Ice” Marcin Rogawski PhD @ GMU, Summer 2013 Currently @ Cadence Design Systems San Jose, CA PhD Student

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• Adders used in multiple branches of science & engineering
• Basic building block of more complex arithmetic

computations (multiplication, modular reduction, etc.)

• Need for long-operand adders (≥1024 bits) in cryptography

(RSA, Diffie-Hellman, Elliptic Curve Cryptography, Pairing-Based Cryptography, post-quantum cryptography)

• FPGAs contain special dedicated resources (fast carry

chains) supporting fast addition, but only for operands in the range of 32-64 bits.

Motivation

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Fast Carry Chains of Modern FPGAs

cin b0 b1 a1 a0

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s FA a0 b0 a1 b1 LUT 1 cout s

1

s s

a) b)

LUT 1 LUT LUT cin cout FA

Xilinx FPGAs Altera FPGAs

• Minimize delays
• Save reconfigurable resources

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Parallel Prefix Network (PPN) Adder

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Parallel Prefix Network – Major Concept (1)

Given: (gn-1, pn-1) …. (g2, p2) (g1, p1) (g0, p0) Generate-propagate signals for each bit position Calculate (in parallel): Generate-propagate signals for each block of bits starting at position 0 (g[0,n-1], p[0,n-1]) …. (g[0,2], p[0,2]) (g[0,1], p[0,1]) (g[0,0], p[0,0])

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Parallel Prefix Network – Major Concept (2)

Calculate:

pci = g[0,i-1] + c0p[0,i-1]

Assuming c0 = 0 (no need to cascade adders that are already very long):

pci = g[0,i-1]

where i=1..n Projected carry at position i

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Kogge-Stone PPN

• Minimum Latency (log2N)
• Large Area

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Brent-Kung PPN

• Good trade-off between Latency (2 log2N – 2) and Area

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Parallel Prefix Network (PPN) Adder in FPGA

• All logic must be implemented using LUTs!
• Large PPN required (e.g., n=1024)

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Our High-Radix Parallel Prefix Network Adder

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GPS: Generate-Propagate-Sum in Xilinx FPGAs

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S: Sum unit in Xilinx FPGAs

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Our High-Radix Parallel Prefix Network Adder

• GPS and S units implemented using Fast Carry Chains
• The size of PPN reduced from n=1024 to N=1024/w

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General Construction for the Modular Adder

R

n

2 −P

n n n n n

0 1

n n n

B A

cout#2 cout#1

R = A + B mod P R = A + B – P when A + B ≥ 2n > P (cout#1)

• r

A + B – P ≥ 0 (cout#2) R = A + B

• therwise

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Our Construction for the High-Radix PPN Modular Adder

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spc

1

spc

N−1

fpN−1

N−1

fg fpcN−1 fpc1

w

1

1

sg GPS

w

1 sg

w

1

N−1

sg spN−1

w w

GPS

w w w w

GPS fg

w w w w

fpcN spc

N N−2

fg fg

N−1

fg

w w

GPS

w

fpN−1 GPSc GPSc

w w w

IP

w N−1

IP

1

IP

S S

w

sp

N−1

sg spN−1 sg 1 spc sp1 sp0 sel fpc1

1

1 fpc spcN−1

N−1

sel sel fp

1 1

fg fp0 fp PPN PPN R R R A B A B B A

1 1 N−1 N−1 N−1

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GPSc: Generate-Propagate-Sum with carry

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Our Construction for the High-Radix PPN Modular Adder

1

spc

1

spc

N−1

fpN−1

N−1

fg fpcN−1 fpc1

w

1

1

sg GPS

w

1 sg

w

1

N−1

sg spN−1

w w

GPS

w w w w

GPS fg

w w w w

fpcN spc

N N−2

fg fg

N−1

fg

w w

GPS

w

fpN−1 GPSc GPSc

w w w

IP

w N−1

IP

1

IP

S S

w

sp

N−1

sg spN−1 sg 1 spc sp1 sp0 sel fpc1

1

1 fpc spcN−1

N−1

sel sel fp

1 1

fg fp0 fp PPN PPN R R R A B A B B A

1 1 N−1 N−1 N−1

Two additions: Ÿ Ÿ overlapped in time Ÿ Ÿ sharing resources (S units)

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Target FPGA Families

Technology ¡ Low-­‑cost ¡ High-­‑ performance ¡ 65 ¡nm ¡ Virtex-­‑5 ¡ 45 ¡nm ¡ Spartan-­‑6 ¡ Technology ¡ Low-­‑cost ¡ High-­‑ performance ¡ 65 ¡nm ¡ Stra2x ¡III ¡ 40 ¡nm ¡ Cyclone ¡IV ¡

Xilinx FPGAs Altera FPGAs

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Design Flow

RTL Design VHDL ¡Code ¡ Option Optimization & Parameter Exploration FPGA ¡Tools ¡ Netlist ¡

Post ¡ Place ¡& ¡Route ¡ Results ¡

Functional Verification Timing Verification SpecificaEon ¡ Test ¡Vectors ¡

GMU ATHENa (FPL 2010)

ATHENa used to simplify parameter exploration (multiple values of generics) and option optimization for both Xilinx and Altera FPGAs

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Choosing the Best PPN & Word Size Adders – Altera Cyclone IV

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Choosing the Best PPN & Word Size Adders – Xilinx Spartan 6

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Choosing the Best PPN & Word Size Modular Adders – Altera Cyclone IV

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Choosing the Best PPN & Word Size Modular Adders – Xilinx Spartan 6

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The Best Choices of PPN Type & Word Size

Adders Modular Adders

Family PPN (w, N) PPN Word Size

Cyclone IV KS (16, 64) KS (16, 64) Stratix III BK (16, 64) BK (16, 64) Spartan 6 BK (32, 32) KS (128, 8) Virtex 5 KS (16, 64) KS (64, 16) KS: Kogge-Stone Parallel Prefix Network BK: Brent-Kung Parallel Prefix Network w – word size N – size of PPN

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The Best Long-Operand Adders Proposed to Date

H.D. Nguyen, B. Pasca, T.B. Preuβer, FPGA-Specific Arithmetic Optimizations of Short-Latency Adders FPL 2011, Chania, Greece

• Adders based on Carry-Select Architecture

(rather than PPN Architecture)

• Three specific architectures proposed
• AAM: Add-Add-Multiplex
• CAI: Compare-Add-Increment
• CCA: Compare-Compare-Add
• Limited results (only Virtex 5) included in the original paper
• AAM architecture re-implemented and results collected

for different FPGAs

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Comparison with Other Adders – Virtex 5

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Comparison with Other Adders – Virtex 5

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Comparison with Other Adders – Spartan 6

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Comparison with Other Adders – Spartan 6

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Comparison with Other Adders – Cyclone IV

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Comparison with Other Adders – Stratix III

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Comparison Between Modular Adders Xilinx Virtex 5

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Comparison Between Modular Adders Xilinx Virtex 5

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Comparison Between Modular Adders Xilinx Spartan 6

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Comparison Between Modular Adders Xilinx Spartan 6

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Comparison Between Modular Adders Altera Stratix III

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Comparison Between Modular Adders Altera Stratix III

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Comparison Between Modular Adders Altera Cyclone IV

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Comparison Between Modular Adders Cyclone IV

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Modular Adder/Subtractor

cout#2 n

2 −P 0 1

n n n n n n n n n n n n n n n n

0 1 0 1 0 1

n n n n n

0 1

n

2 −P P

n n n n n n n

B A R

cout#2 cout#1

A P R 1 B

n

R

SUB SUB

A 1 B

n n

cout#1

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Overhead of Modular Adder/Subtractor

Altera Cyclone IV

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Overhead of Modular Adder/Subtractor

Altera Stratix III

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Overhead of Modular Adder/Subtractor

Xilinx Spartan 6

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Overhead of Modular Adder/Subtractor

Xilinx Virtex 5

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Proposed New Dedicated Resources of Modern FPGAs

• Dedicated (hardwired) PPNs (Kogge-Stone and/or Brent-Kung)
• Standard sizes (e.g., 32 and/or 64)
• Support fast addition and modular addition for large operand sizes

(as described in this paper)

• Support for fast addition and modular addition of medium
• perand sizes (up to 64), using classical PPN adders
• Pipelined registers that can be activated or bypassed

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• A new family of

High-Radix Parallel Prefix Network Adders using fast carry chains of modern FPGAs

• New family outperforming the best previously known

FPGA-specific adders and modular adders for Xilinx FPGAs

• Very small performance penalty for an extension

to adders/subtractors

• A proposal for embedding medium-size hardwired PPN

structures in the new generations of FPGAs

Conclusions

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• Possible optimizations for Altera FPGAs
• Better (preferably analytical) method of choosing

an optimum word size for

• Other FPGA families
• Other operand sizes
• Optimal method of pipelining for adders and modular adders
• Extended and more detailed proposal of new FPGA

resources supporting fast addition

Future Work

Questions? Thank you!

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Suggestions?

ATHENa: http:/cryptography.gmu.edu/athena CERG: http://cryptography.gmu.edu