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A Model-based Embedded Control Hardware/Software Co-design Approach for Optimized Sensor Selection of Industrial Systems

Kyriakos M. Deliparaschos, Konstantinos Michail, Spyros G. Tzafestas, Argyrios C. Zolotas

23rd Mediterranean Conference on Control and Automation (MED 2015) Torremolinos – SPAIN, 16 – 19 June 2015

Contents

• Introduction and proposed framework
• Electromagnetic suspension (EMS) test case
• FIL and FPGA architecture of LQG controller
• Results
• Conclusions

2

Hardware-in-the-loop (HIL)

• HIL widely used in developing/testing

complex real-time control systems

• Simulation model of the plant is part of

the test platform

• Model-based embedded control hw/sw

co-design approach is followed

• System is realized in soft form, i.e.,

using a high-level language (e.g., MATLAB/Simulink)

• In embedded control system: the

model of the plant (realized on sw) interfaces with the actual controller (implemented on hw) via a communication link

Software-based plant model Hardware-based controller Communication protocol (Ethernet link) Physical process FPGA

3

System-level design

• Control design
• Maintain performance

in an integrated framework

• Even if sensors/

actuators given, which may be the “better” set for the above?

System

Uncertainties

Faults Faults

Disturbances Non-linearities Inherently Unstable

4

Electromagnetic suspension test case

Suspended mass (m)

Mg F

Track Electromagnet Pole Power Amplifier

Driving Signal Flux circulation Airgap

• Vert. Accleration
• Vert. Velocity

Current

K

Controller

• EMS serves two

purposes:

• Supports the

vehicle and passengers

• Ensures proper ride

quality

5

Input excitations and performance specs

Deterministic Stochastic

Test inputs

6

cles, & & & & = = φ φ − < − Table 1 MAGLEV suspension constraints Constraints Value RMS acceleration ) ( rms z & & < 0.5ms-2 RMS gap variation, ) ) ((

rms t

z z − < 5mm Control effort, ) ( rms u < 300V(3IoRo) Air gap deviation, ) ) ((

p t

z z − < 7.5mm Control effort, (up) < 300V(3IoRo) Settling time, (ts) < 3s Steady state error ( )

ss

e =0 −

η

ω ω + = + + = &

Performance specs

• aiming for minimal set of sensors

Design procedure

• Overall control constraint

violation function

• If Ω=0 then performance

requirements are satisfied. If Ω≠0 then there is some violation of control constraints

• Controller selection criteria



 for final selection of controller

7 Initialise Algorithm Select first Sensor set

Optimize closed-loop performance by using Genetic Algorithms

Select the ‘‘best’’ controller More sensor sets? Yes Select the best sensor set No

Optimized sensor selection for the EMS

LQR

With LQG

Similar response Test

8

LQR full state

maintaining performance

FPGA-in-the-loop (FIL) framework for optimized sensor selection

• FPGA-targetted HIL

technique -> FPGA-in- the-loop (FIL)

• FIL schematic for EMS
• Out of all available
• utputs, yf , feed the

best sensor set yo into the FIL-based LQG.

Physical Process (Non-linear MAGLEV suspension model)

+

LQR KBE

Optimised sensor selection

Software model (MAGLEV)

• Hardware model (LQG Controller)

+ + + + + + +

Network fabric

9

LQG design architecture

• A detailed LQG core

model using explicitly scalar buses

• 3 sensor measurements

(y1, y2, y3)

K*u

Estimated states Control input Sensor measurements

K*u K*u K*u velocity gain K*u current gain fixpt scaling K*u airgap gain K*u

(a)

10

Hardware Description Language (HDL) code generation

• LQG conversion from floating-point

domain to fixed-point domain

• MathWorks HDL Coder tool used to

automate and speed up the process

• f translating high level simulation

model into equivalent Register Transfer Level (RTL) HDL description (i.e., VHDL)

• HDL Coder limitations in handling

multi dimension matrices, hence:
 
 Detailed LQG core model using explicitly scalar buses was developed prior to HDL translation (i.e., architecture of A

3x3 sub-block)

1 LIBRARY IEEE ; 2 USE IEEE . std_logic_1164 .ALL; 3 USE IEEE . numeric_std .ALL; 4 5 ENTITY LQG IS 6 PORT( clk : IN std_logic ; 7 r s t : IN std_logic ; 8 clk_en : IN std_logic ; 9 c o n t r o l _ i n : IN std_logic_vector (25 DOWNTO 0) ; − − sfix26_En19 10 i _ i n p u t _ i n : IN std_logic_vector (31 DOWNTO 0) ; − − sfix32_En28 11 b_in : IN std_logic_vector (31 DOWNTO 0) ; − − sfix32_En35 12 a_in : IN std_logic_vector (31 DOWNTO 0) ; − − sfix32_En31 13 ce_out : OUT std_logic ; 14 uc_d_op : OUT std_logic_vector (34 DOWNTO 0) ; − − sfix35_En27 15 i_op : OUT std_logic_vector (35 DOWNTO 0) ; − − sfix36_En24 16 z_dot_op : OUT std_logic_vector (35 DOWNTO 0) ; − − sfix36_En23 17 gap_op : OUT std_logic_vector (34 DOWNTO 0) ; − − sfix35_En23 18 igap_op : OUT std_logic_vector (35 DOWNTO 0) − − sfix36_En23 19 ) ; 20 END LQG;

Out3 Out2 Out1

A(3,3) A(3,2) A(3,1) A(2,3) A(2,2) A(2,1) A(1,2) A(1,1)

In3 In2 In1

A(1,3)

(b)

11

HW/SW co-design FPGA flow

• Top-down method: for the design

process of the LQG controller

• Model specifications and system

requirements -> high level functional system model -> conversion to fixed-point 
 (pre- FPGA implementation)

FPGA device configuration Model specifications Algorithmic analysis and implementation in floating point Place and Route Model conversion in fixed point Implementation in RTL VHDL Logic synthesis Testbench Algorithm RTL design Stimuli Results + - Diff Co-simulation with MATLAB HDL Simulator Testbench Algorithm ML605 FPGA Board Stimuli Results + - Diff FPGA-in-the-Loop simulation Integration with peripheral cores (Ethernet MAC, DCM) Ethernet link

Discretization Quantization

Implementation on FPGA

MATLAB FPGA

12

• Co-simulation of RTL model and

fixed-point Simulink model using MathWorks HDL Verifier and Mentor Modelsim simulator

• Compare system implemented on

FPGA chip (in real time) using a cycle accurate Simulink model forming a FIL setup

Design utilization results

• FPGA design utilization

Summary for the LQG controller with current/flux/ accel and flux modules

• FIL implemented on a Xilinx

Virtex-6 ML605 development board utilizing a Xilinx Virtex-6 device (XC6VLX240T-1FFG1156)

• LQG and the peripheral cores

synthesized via Xilinx Synthesis Tool (XST)

Module(iba) Slices Slice Reg. LUTs DSP48E1 LQG 0/265 0/113 0/884 0/73 KBE 49/221 77/77 170/717 1/50 Ad 67/67 0/0 221/221 27/27 Cd 30/30 0/0 99/99 14/14 Kd

lqg

75/75 0/0 227/227 8/8 LQR 44/44 36/36 167/167 23/23 Module(b) Slices Slice Reg. LUTs DSP48E1 LQG 0/205 0/111 0/696 0/69 KBE 41/161 75/75 143/529 1/46 Ad 69/69 0/0 220/220 27/27 Cd 12/12 0/0 30/30 6/6 Kd

lqg

39/39 0/0 136/136 12/12 LQR 44/44 36/36 167/167 23/23

D of available Slices

0.74 0.13 0.19 0.09 0.21 0.12 0.54 0.12 0.17 0.02 0.12 0.12 LQG KBE LQR 0.2 0.4 0.6 0.8

D of available Slice Registers

0.04 0.03 0.00 0.00 0.00 0.01 0.04 0.02 0.00 0.00 0.00 0.01 LQG KBE LQR 0.01 0.02 0.03 0.04

D of available LUTs

0.59 0.11 0.15 0.07 0.15 0.11 0.47 0.10 0.15 0.02 0.09 0.11 LQG KBE LQR 0.2 0.4 0.6 0.8

D of available DSP48E1

9.51 0.13 3.52 1.82 1.04 2.99 8.98 0.13 3.52 0.78 1.56 2.99 LQG KBE LQR 2 4 6 8 10 12

13

Design speed achievement*

• 29.1MHz clock operating freq (current/flux/accel)
• 30.5MHz clock operating freq (flux)
• Map and place and route effort was set to medium

*according to post-place and route timing report on Xilinx ISE 13.3

14

EMS performance

• Airgap error with flux

and current/flux/accel

• State estimation with

flux (deterministic input)

• Continuous-time vs. FIL

(discrete/quantized)

1 2 3 4 5 6 2 4 1 2 3 4 5 6 2 4 6 x 10

−4

6 x 10

−4

1 2 3 4 5 6 2 4 Current with LQR Estimated current with FIL 1 2 3 4 5 6 0.2 0.4 0.6 Velocity with LQR Estimated velocity with FIL 1 2 3 4 5 6 2 4 6 x 10

−3

Airgap with LQR Estimated airgap with FIL

15

Conclusions

• Embedded control system for EMS sensor optimization via FIL
• Matlab/Simulink hosts the physical process and LQG

implemented on FPGA

• The design approach followed a fusion of system modeling and

hw/sw co-design

• Economical FPGA implementation due to early quantization

analysis in the design process

• Results on two sensor set examples and illustration of FIL

advances in accelerating system validation

16

A Model-based Embedded Control Hardware/Software Co-design Approach for Optimized Sensor Selection of Industrial Systems

Kyriakos M. Deliparaschos, Konstantinos Michail, Spyros G. Tzafestas, Argyrios C. Zolotas

23rd Mediterranean Conference on Control and Automation (MED 2015) Torremolinos – SPAIN, 16 – 19 June 2015