A Data Remanence based Approach to Generate 100% Stable Keys from - PowerPoint PPT Presentation

A Data Remanence based Approach to Generate 100% Stable Keys from an SRAM Physical Unclonable Function Muqing Liu, Chen Zhou, Qianying Tang, Keshab K. Parhi and Chris H. Kim University of Minnesota, Twin Cities liux3300@umn.edu International Symposium on Low Power Electronics and Design

Outline • Introduction and Motivation • Proposed Data Remanence based Approach • SRAM PUF Measurement Results • Summary 2

Outline • Introduction and Motivation • Proposed Data Remanence based Approach • SRAM PUF Measurement Results • Summary 3

Key Storage: Flash Memory • Concerns: Process overhead; vulnerable to invasive/semi-invasive attacks. 4

Key Generation: SRAM based PUF Power-up state Uncontrollable process variation WL Stable ‘ 0 ’ Stable ‘ 1 ’ Unstable BLB BL • Strength: No process overhead, negligible implementation effort. 5

Key Generation: SRAM based PUF SRAM array Unique key Row Circuit Stable ‘ 1 ’ Unstable Stable ‘ 0 ’ Column Circuit Ctrl. • Concerns: Intrinsic mismatch of a SRAM cell not always large enough to generate stable responses. 6

Temporal Majority Voting (TMV) • TMV: Repetitively test the PUF responses and take the majority value as the final output. • Cons: Costly and time consuming, hardware overhead, cannot find absolutely stable bits. 6

Outline • Introduction and Motivation • Proposed Data Remanence based Approach • SRAM PUF Measurement Results • Summary 8

Data Remanence based Approach 9

Data Remanence based Approach 65nm LP, 25 o C, TT, simulation VDD SRAM data flips 80 T flip 70 Stronger ‘ 1 ’ Stronger ‘ 0 ’ 60 T flip (a.u.) WL 50 40 30 20 QB 10 Q 0 -25 -15 -5 5 15 25 BLB BL V mismatch (mV) V mismatch • The first few cells to flip after the brief power down period are the most strongly biased cells. 10

Measurement Set Up • PXI based data acquisition system: provides pulsed power supply and digital signals. • Power supply: stress the chip. • Off-the-shelf SRAM chips: 512 kbit from Microchip Technology. 11

Flip Ratio vs. Power Down Period 12

Cell Flip Map for Writing ‘0’ 5 5 10 Strongest ‘ 1 ’ 10 Row # Row # 15 15 PD=130ms PD=140ms 20 20 25 25 30 30 5 10 15 20 25 30 5 10 15 20 25 30 Column # Column # 5 5 10 10 Row # Row # 15 15 PD=150ms PD=160ms 20 20 25 25 30 30 5 10 15 20 25 30 5 10 15 20 25 30 Column # Column # Data ‘ 1 ’ Data ‘ 0 ’ • Strongest ‘1’ cell always flips. 13

Cell Flip Map for Writing ‘1’ 5 5 10 10 Row # Row # 15 15 PD=130ms PD=140ms 20 20 Strongest ‘ 0 ’ 25 25 30 30 5 10 15 20 25 30 5 10 15 20 25 30 Column # Column # 5 5 10 10 Row # Row # 15 15 PD=150ms PD=160ms 20 20 25 25 30 30 5 10 15 20 25 30 5 10 15 20 25 30 Column # Column # Data ‘ 1 ’ Data ‘ 0 ’ • Strongest ‘0’ cell always flips. 14

SRAM Data Remanence for Data ‘1’ 0k Data ‘ 0 ’ Bit index (sorted by 100k 0.0k retention time) 128 bits 0.2k 256 bits 200k 0.4k 512 bits 300k 0.6k Target pulse width 0.8k 400k Data ‘ 1 ’ 1.0k100 125 150 175 200 225 500k 100 225 350 475 600 Power Down Period (ms) • Bit index is sorted from strongest ‘0’ to strongest ‘1’. 15

SRAM Data Remanence for Data ‘0’ 0k Bit index (sorted by Data ‘ 0 ’ 100k retention time) 523.5k 200k 523.7k 512 bits Target pulse width 523.9k 300k 256 bits 524.1k 128 bits 400k 524.3k 100 125 150 175 200 225 Data ‘ 1 ’ 500k 100 225 350 475 600 Power Down Period (ms) • Bit index is sorted from strongest ‘0’ to strongest ‘1’. 16

Data Remanence and PUF Test Flow Data Remanence SRAM PUF Operation Test Enrollment Key Generation Write all ‘ 1 ’ or ‘ 0 ’ Turn off power, Write all ‘ 1 ’ or ‘ 0 ’ Power on SRAM wait for time T Turn on power, Turn off power, Stable bit read out data wait for T require location Record flip Turn on power, Response (Keys) location(s) read out data Yes Record flip T min < T < T max ? locations No Store stable Key T require = T length bit location 17

Outline • Introduction and Motivation • Proposed Data Remanence based Approach • SRAM PUF Measurement Results • Summary 18

Uniqueness of Generated Key 256-bit Key Chip 1 Chip 2 Chip 3 Chip 4 Data ‘ 1 ’ Data ‘ 0 ’ • Average inter-chip Hamming distance is 0.4935 (ideally close to 0.5). 19

PUF Stability: Temperature Effect Data Remanence based Approach T = -10 o C T = 25 o C T = 80 o C Power up ramp time = 0.78V/µs Data ‘ 1 ’ Data ‘ 0 ’ • Average intra-chip Hamming distance is 0 under different temperatures. 20

PUF Stability: Temperature Effect TMV Selected Stable Cells T = -10 o C T = 25 o C T = 80 o C Power up ramp time = 0.78V/µs Data ‘ 1 ’ Data ‘ 0 ’ Unstable cell • Average intra-chip Hamming distance is 0.0026. 21

PUF Stability: Temperature Effect Randomly Selected Cells T = -10 o C T = 25 o C T = 80 o C Power up ramp time = 0.78V/µs Data ‘ 1 ’ Data ‘ 0 ’ Unstable cells • Average intra-chip Hamming distance is 0.081. 22

PUF Stability: Power Up Ramp Effect Data Remanence based Approach Power up ramp Power up ramp Power up ramp time = 0.78V/µs time = 1.25V/µs time = 8.33V/µs T = -10 o C Data ‘ 1 ’ Data ‘ 0 ’ • Average intra-chip Hamming distance is 0 under different power ramp up rates. 23

PUF Stability: Power Up Ramp Effect TMV Selected Stable Cells Power up ramp Power up ramp Power up ramp time = 0.78V/µs time = 1.25V/µs time = 8.33V/µs T = -10 o C Data ‘ 1 ’ Data ‘ 0 ’ Unstable cells • Average intra-chip Hamming distance is 0.003. 24

PUF Stability: Power Up Ramp Effect Randomly Selected Cells Power up ramp Power up ramp Power up ramp time = 0.78V/µs time = 1.25V/µs time = 8.33V/µs T = -10 o C Data ‘ 1 ’ Data ‘ 0 ’ Unstable cells • Average intra-chip Hamming distance is 0.031. 25

Overall PUF Stability Test This work TMV selected stable cells Randomly selected cells Power up ramp Power up ramp Power up ramp Power up ramp Power up ramp Power up ramp Power up ramp Power up ramp Power up ramp time = 0.78V/µs time = 1.25V/µs time = 8.33V/µs time = 0.78V/µs time = 1.25V/µs time = 8.33V/µs time = 0.78V/µs time = 1.25V/µs time = 8.33V/µs T = 80 o C T = 25 o C T = -10 o C Avg. Intra-chip Hamming distance = 0.0712 Avg. Intra-chip Hamming distance = 0 Avg. Intra-chip Hamming distance = 0.0091 Data ‘ 0 ’ Data ‘ 1 ’ Unstable cells

PUF Stability: Aging Effect Stress: 1.5*V nom , Measure: V nom , 25 o C 0.2 Intra-chip Hamming Random (256, 512, 1024-bit) 0.15 Distance 0.1 TMV (256, 512, 1024-bit) 0.05 This work (256, 512, 1024-bit) 0 0 10 20 30 40 50 60 70 80 Stress Time (hrs) • 100% of the cells selected using proposed technique remain stable under device aging test. 27

Summary • Proposed a data remanence based technique by momentarily shutting down the power supply to select the most stable cells as the key. • Measurement results confirmed 100% key stability under different conditions: – Temperature variations. – Power ramp up rate variations. – Device aging effect. Acknowledgements This research has been supported by the National Science Foundation under grant number CNS-1441639 and the semiconductor research corporation under contract number 2014-TS-2560. 28