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Oct 26, 2022 212 likes •496 views

A Data Remanence based Approach to Generate 100% Stable Keys from an SRAM Physical Unclonable Function Muqing Liu, Chen Zhou, Qianying Tang, Keshab K. Parhi and Chris H. Kim University of Minnesota, Twin Cities liux3300@umn.edu International

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SLIDE 1

International Symposium on Low Power Electronics and Design

A Data Remanence based Approach to Generate 100% Stable Keys from an SRAM Physical Unclonable Function

Muqing Liu, Chen Zhou, Qianying Tang, Keshab K. Parhi and Chris H. Kim

University of Minnesota, Twin Cities

liux3300@umn.edu

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SLIDE 2
  • Introduction and Motivation
  • Proposed Data Remanence based Approach
  • SRAM PUF Measurement Results
  • Summary

2

Outline

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SLIDE 3
  • Introduction and Motivation
  • Proposed Data Remanence based Approach
  • SRAM PUF Measurement Results
  • Summary

3

Outline

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SLIDE 4

4

Key Storage: Flash Memory

  • Concerns: Process overhead; vulnerable to

invasive/semi-invasive attacks.

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SLIDE 5

5

Key Generation: SRAM based PUF

  • Strength: No process overhead, negligible

implementation effort.

Power-up state Uncontrollable process variation

WL BL BLB Stable ‘1’ Stable ‘0’ Unstable

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SLIDE 6

6

Key Generation: SRAM based PUF

Unique key SRAM array

Column Circuit Row Circuit

Ctrl.

Stable ‘1’ Unstable Stable ‘0’

  • Concerns: Intrinsic mismatch of a SRAM cell not

always large enough to generate stable responses.

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SLIDE 7

Temporal Majority Voting (TMV)

  • TMV: Repetitively test the PUF responses and

take the majority value as the final output.

  • Cons: Costly and time consuming, hardware
  • verhead, cannot find absolutely stable bits.

6

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SLIDE 8
  • Introduction and Motivation
  • Proposed Data Remanence based Approach
  • SRAM PUF Measurement Results
  • Summary

8

Outline

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SLIDE 9

9

Data Remanence based Approach

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SLIDE 10

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Data Remanence based Approach

10 20 30 40 50 60 70 80

  • 25
  • 15
  • 5

5 15 25

Tflip (a.u.)

Vmismatch (mV)

65nm LP, 25oC, TT, simulation Stronger ‘0’ Stronger ‘1’

WL BL BLB Q QB Vmismatch Tflip

VDD SRAM data flips

  • The first few cells to flip after the brief power

down period are the most strongly biased cells.

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SLIDE 11
  • PXI based data

acquisition system: provides pulsed power supply and digital signals.

  • Power supply: stress

the chip.

  • Off-the-shelf SRAM

chips: 512 kbit from Microchip Technology.

11

Measurement Set Up

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SLIDE 12

Flip Ratio vs. Power Down Period

12

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SLIDE 13

Strongest ‘1’ 5 10 15 20 25 30 5 10 15 20 25 30 5 10 15 20 25 30 5 10 15 20 25 30 5 10 15 20 25 30 5 10 15 20 25 30 5 10 15 20 25 30 5 10 15 20 25 30 Data ‘1’ Data ‘0’

PD=130ms PD=150ms PD=140ms PD=160ms Row # Row # Row # Row # Column # Column # Column # Column #

13

Cell Flip Map for Writing ‘0’

  • Strongest ‘1’ cell always flips.
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SLIDE 14

14 Strongest ‘0’ 5 10 15 20 25 30 5 10 15 20 25 30 5 10 15 20 25 30 5 10 15 20 25 30 5 10 15 20 25 30 5 10 15 20 25 30 5 10 15 20 25 30 Data ‘1’ Data ‘0’ 5 10 15 20 25 30

PD=130ms PD=150ms PD=140ms PD=160ms Row # Row # Row # Row # Column # Column # Column # Column #

Cell Flip Map for Writing ‘1’

  • Strongest ‘0’ cell always flips.
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SLIDE 15

15

  • Bit index is sorted from strongest ‘0’ to

strongest ‘1’.

SRAM Data Remanence for Data ‘1’

0.2k 0.4k 0.6k 0.8k 1.0k100 125 150 175 200 225

128 bits 256 bits 512 bits Target pulse width

Bit index (sorted by retention time) Power Down Period (ms)

0.0k 100k 200k 300k 400k 500k

Data ‘1’ Data ‘0’

0k

225 350 475 600 100

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SLIDE 16

16

  • Bit index is sorted from strongest ‘0’ to

strongest ‘1’.

SRAM Data Remanence for Data ‘0’

Bit index (sorted by retention time) Power Down Period (ms)

100k 200k 300k 400k 500k 0k

225 350 475 600 100

100 125 150 175 200 225 523.5k 523.7k 523.9k 524.1k 524.3k

128 bits 256 bits 512 bits Target pulse width

Data ‘0’ Data ‘1’

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SLIDE 17

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Data Remanence and PUF Test Flow

Turn off power, wait for Trequire Turn on power, read out data Record flip locations Response (Keys) Write all ‘1’ or ‘0’ Store stable bit location Stable bit location Power on SRAM Turn off power, wait for time T Turn on power, read out data Record flip location(s) Write all ‘1’ or ‘0’

Data Remanence Test

Trequire = T

SRAM PUF Operation Enrollment Key Generation

Tmin < T < Tmax ? Key length Yes No

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SLIDE 18
  • Introduction and Motivation
  • Proposed Data Remanence based Approach
  • SRAM PUF Measurement Results
  • Summary

18

Outline

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SLIDE 19
  • Average inter-chip Hamming distance is 0.4935

(ideally close to 0.5).

19

Uniqueness of Generated Key

Chip 1

Data ‘1’ Data ‘0’

Chip 2 Chip 3 Chip 4 256-bit Key

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SLIDE 20
  • Average intra-chip Hamming distance is 0 under

different temperatures.

20

PUF Stability: Temperature Effect

T = 80oC T = 25oC T = -10oC

Data Remanence based Approach

Power up ramp time = 0.78V/µs Data ‘0’ Data ‘1’

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SLIDE 21
  • Average intra-chip Hamming distance is 0.0026.

21

T = 80oC T = 25oC T = -10oC

TMV Selected Stable Cells

Power up ramp time = 0.78V/µs Data ‘0’ Data ‘1’ Unstable cell

PUF Stability: Temperature Effect

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SLIDE 22

22

T = 80oC T = 25oC

Randomly Selected Cells

Power up ramp time = 0.78V/µs Data ‘0’ Data ‘1’ Unstable cells T = -10oC

PUF Stability: Temperature Effect

  • Average intra-chip Hamming distance is 0.081.
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SLIDE 23

23

Data Remanence based Approach

T = -10oC Power up ramp time = 0.78V/µs Power up ramp time = 1.25V/µs Power up ramp time = 8.33V/µs Data ‘0’ Data ‘1’

  • Average intra-chip Hamming distance is 0 under

different power ramp up rates.

PUF Stability: Power Up Ramp Effect

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SLIDE 24

24

TMV Selected Stable Cells

T = -10oC Power up ramp time = 0.78V/µs Power up ramp time = 1.25V/µs Power up ramp time = 8.33V/µs Data ‘0’ Data ‘1’ Unstable cells

  • Average intra-chip Hamming distance is 0.003.

PUF Stability: Power Up Ramp Effect

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SLIDE 25

25

Randomly Selected Cells

T = -10oC Power up ramp time = 0.78V/µs Power up ramp time = 1.25V/µs Power up ramp time = 8.33V/µs Data ‘0’ Data ‘1’ Unstable cells

  • Average intra-chip Hamming distance is 0.031.

PUF Stability: Power Up Ramp Effect

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SLIDE 26

TMV selected stable cells

Unstable cells Data ‘0’ Data ‘1’

Randomly selected cells

T = 80oC T = 25oC T = -10oC

This work

Power up ramp time = 0.78V/µs Power up ramp time = 1.25V/µs Power up ramp time = 8.33V/µs

  • Avg. Intra-chip Hamming distance = 0
  • Avg. Intra-chip Hamming distance = 0.0091
  • Avg. Intra-chip Hamming distance = 0.0712

Power up ramp time = 0.78V/µs Power up ramp time = 1.25V/µs Power up ramp time = 8.33V/µs Power up ramp time = 0.78V/µs Power up ramp time = 1.25V/µs Power up ramp time = 8.33V/µs

Overall PUF Stability Test

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SLIDE 27

27

  • 100% of the cells selected using proposed

technique remain stable under device aging test.

Stress Time (hrs)

10 20 30 40 50 60 70 80 0.05 0.1 0.15 0.2

Intra-chip Hamming Distance

Stress: 1.5*Vnom, Measure: Vnom, 25oC This work (256, 512, 1024-bit) TMV (256, 512, 1024-bit) Random (256, 512, 1024-bit)

PUF Stability: Aging Effect

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SLIDE 28
  • Proposed a data remanence based technique by

momentarily shutting down the power supply to select the most stable cells as the key.

  • Measurement results confirmed 100% key stability under

different conditions: – Temperature variations. – Power ramp up rate variations. – Device aging effect.

28

Summary

This research has been supported by the National Science Foundation under grant number CNS-1441639 and the semiconductor research corporation under contract number 2014-TS-2560.

Acknowledgements