5th Generation Touchscreen Controller for Mobile Phones and Tablets - PowerPoint PPT Presentation

5th Generation Touchscreen Controller for Mobile Phones and Tablets Hot Chips 2013 Milton Ribeiro John Carey August, 2013

Design Goals � Quick design of derivatives � Platform-based design � Scalable analog front-end (AFE) � Scalable DSP datapath � Flexible hardware platform � Superior noise suppression performance � Display noise: DCV com, AC Vcom, OLED Display noise: DCV com, AC Vcom, OLED � Finger-couple noise (charger noise): > 40 Vpp � Innovation acceleration thru flexible hardware � Glove and hover support � Robust water rejection and wet finger tracking � Passive stylus support � Active stylus support 2

Architectural Elements (I) � CPU � Cortex M0 @ 48 MHz � Support for flash memory (scalable) � Support for SRAM (scalable) � Support for ROM memory (scalable) � Low-power microcontroller infrastructure � Support for Hibernate, Deep-sleep, Sleep, Idle and Active modes Support for Hibernate, Deep-sleep, Sleep, Idle and Active modes � On-chip power generation (LDO and voltage pump) � Robust analog front-end (AFE) � Large on-chip integration capacitors � Signal attenuators in each channel � Large charge handling capability: > 240 pC per cycle � High-speed operation: up to 1 Msps 3

Architectural Elements (II) � High-voltage signal generation � On-chip charge pump for 10V generation � Configurable DSP datapath � Low-power linear and non-linear filtering � FIR and window filters � Median filtering � Digital quadrature demodulation for active stylus � Digital quadrature demodulation for active stylus � Real-time noise-metrics � 2D image processing algorithms: filtering, peak-search, etc. � Table-driven sequencer � Flexible timing generation enables advanced scanning modes � Easy integration with DDI ASICs for incell and oncell integration 4

Gen5 Architecture Overview TSS HW acceleration CE HW acceleration RX RX Channels Mux + pads om Panel AHB I/F ARM CM0, SEQ To / From P RX / TX Mux SRAM SRAM Infra Infra IDAC IDAC Registers Registers ROM (support, test) Flash VREF etc Shield TX Driver TX Pump Slew Control VCCTX ext VDDA or C ext 5

TSG5_L Touchscreen Controller CPU Subsystem � TSG5-L ASSP ARM CM0 M0S8 Architecture SWD/TC SPCIF � ARM Debug Cortex FLASH SRAM ROM 32-bit M0 64 kB 12 kB 8 kB � Low power 48 MHz AHB-Lite FAST MUL Read Accelerator SRAM Controller ROM Controller NVIC, IRQMX � CY S8 Process System Resources Power � 130nm System Interconnect (Single Layer AHB) Sleep Control WIC Peripherals POR LVD � FLASH REF BOD PCLK Peripheral Interconnect (MMIO) PWRSYS NVLatches � 10V capable Clock TSS-G5 Clock Control 512B WDT IMO ILO TSS-IF IOSS GPIO (2x ports) Serial Comm Capacitance Map Noise Map Reset Reset Control Sequencer XRES Channel Engine, Deconvolution, Local Max ) Test X p 21x RX Channels m T DFT Logic (incl. LX) S u DFT Analog T p ( 58x TXRX Power Modes High Speed I/O Matrix Active/Sleep Deep Sleep Hibernate 4x GPIO, 2x SIO IO Subsystem 6

TSG5 RX AFE Architecture Per-edge signal processing, 40V charger noise Per-channel Single-edge Per-channel H/W Baselining Integrator ADC Atten. Touch Sensor 8b SAR VX VX Vref 7

Gen5: Application of Flexible Timing Generation Removes 3 rd /6 th /9 th harmonics, e.g. for F TX =100kHz that ’ s 300/600/900kHz � D67 = integrate for 2/3 of the period, or 67% duty cycle � � Esp. effective for slow panels. 1.5x noise immunity for all the higher-freq noise Channel response @ F TX =100kHz With D67 F TX 3F TX 5F TX 7F TX 9F TX Without Duracell Charger 8

Gen 4/5 Comparison Feature Gen 4 Gen 5 TX drive (square wave) 2.6-10V 2.6-10V,C ext or V TX MPTX 4 Full axis � 300kHz � 500kHz TX frequency � 2 TX (sub-int) Max RX sample rate ½ TX (=per edge) HW Baseline Cal. Yes Yes, larger Max RX charge 8pC/edge 30..200pC/edge 10b SAR, 10b SAR, RX ADC 8b SAR per ch. shared LX channel Yes Yes LCD sync Int/ext Int/ext Signal processing M0 CPU, 32b CPU or CE Noise metric CPU CPU or CE Autom. sequencing Yes Yes, table driven Self & Mutual Cap Yes Yes V DDD 1.71 – 5.5V 1.71-5.5V V CCA (core) 2.4V 2.65-5.5V 9

Current Status and Future Developments � Smartphone and tablet devices available today � TGS5_M: 36 I/Os and 11 channels, supporting phones up to 4.7” � TSG5_L: 58 I/Os and 21 channels, supporting phones and tablets up to 9” � Large tablet and notebook device available later � Large tablet and notebook device available later in the year 10

Thank You Thank You mrib@cypress.com jonc@cypress.com 11