SLIDE 1
[537] TLBs
Tyler Harter 9/21/14
Overview
Review Paging TLBs (Chapter 18) TLB measurement demo (if time)
[537] TLBs Tyler Harter 9/21/14 Overview Review Paging TLBs - - PowerPoint PPT Presentation
[537] TLBs Tyler Harter 9/21/14 Overview Review Paging TLBs - - PowerPoint PPT Presentation
[537] TLBs Tyler Harter 9/21/14 Overview Review Paging TLBs (Chapter 18) TLB measurement demo (if time) Review: Paging 0 KB 1 5 4 P1 pagetable PT PT 4 KB 6 2 3 P2 pagetable P1 8 KB P2 Physical Virtual 12 KB P2 16
SLIDE 2
SLIDE 3
Review: Paging
SLIDE 4
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
PT
P1 pagetable
1 5 4 …
P2 pagetable
6 2 3 … P2
28 KB
Virtual Physical
SLIDE 5
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
PT
P1 pagetable
1 5 4 …
P2 pagetable
6 2 3 … P2
28 KB
Virtual Physical load 0x0000
what must you know?
SLIDE 6
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
PT
P1 pagetable
1 5 4 …
P2 pagetable
6 2 3 … P2
28 KB
PTBR Virtual Physical load 0x0000
SLIDE 7
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
Virtual Physical
PT
P1 pagetable
1 5 4 …
P2 pagetable
6 2 3 … P2
28 KB
load 0x0000 PTBR load 0x0800 (2KB)
SLIDE 8
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
Virtual Physical
PT
P1 pagetable
1 5 4 …
P2 pagetable
6 2 3 … P2
28 KB
load 0x0000 PTBR load 0x0800 (2KB) load 0x6000 (24KB)
SLIDE 9
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
Virtual Physical
PT
P1 pagetable
1 5 4 …
P2 pagetable
6 2 3 … P2
28 KB
load 0x0000 PTBR load 0x0800 (2KB) load 0x6000 (24KB)
SLIDE 10
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
Virtual Physical
PT
P1 pagetable
1 5 4 …
P2 pagetable
6 2 3 … P2
28 KB
load 0x0000 PTBR load 0x0800 (2KB) load 0x6000 (24KB)
SLIDE 11
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
Virtual Physical
PT
P1 pagetable
1 5 4 …
P2 pagetable
6 2 3 … P2
28 KB
load 0x0000 PTBR load 0x0800 (2KB) load 0x6000 (24KB)
SLIDE 12
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
Virtual Physical
PT
P1 pagetable
1 5 4 …
P2 pagetable
6 2 3 … P2
28 KB
load 0x0000 PTBR load 0x0800 (2KB) load 0x6000 (24KB) load 0x1444
what must you know?
SLIDE 13
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
Virtual Physical
PT
P1 pagetable
1 5 4 …
P2 pagetable
6 2 3 … P2
28 KB
load 0x0000 PTBR load 0x0800 (2KB) load 0x6000 (24KB) load 0x1444
assume 8-byte PTEs
SLIDE 14
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
Virtual Physical
PT
P1 pagetable
1 5 4 …
P2 pagetable
6 2 3 … P2
28 KB
load 0x0000 PTBR load 0x0800 (2KB) load 0x6000 (24KB) load 0x1444 load 0x0808
SLIDE 15
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
Virtual Physical
PT
P1 pagetable
1 5 4 …
P2 pagetable
6 2 3 … P2
28 KB
load 0x0000 PTBR load 0x0800 (2KB) load 0x6000 (24KB) load 0x1444 load 0x0808 load 0x2444
SLIDE 16
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
Virtual Physical
PT
P1 pagetable
1 5 4 …
P2 pagetable
6 2 3 … P2
28 KB
load 0x0000 PTBR load 0x0800 (2KB) load 0x6000 (24KB) load 0x1444 load 0x0808 load 0x2444
SLIDE 17
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
Virtual Physical
PT
P1 pagetable
1 5 4 …
P2 pagetable
6 2 3 … P2
28 KB
load 0x0000 PTBR load 0x0800 (2KB) load 0x6000 (24KB) load 0x1444 load 0x0808 load 0x2444
SLIDE 18
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
Virtual Physical
PT
P1 pagetable
1 5 4 …
P2 pagetable
6 2 3 … P2
28 KB
load 0x0000 PTBR load 0x0800 (2KB) load 0x6000 (24KB) load 0x1444 load 0x0808 load 0x2444 load 0x1444
SLIDE 19
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
Virtual Physical
PT
P1 pagetable
1 5 4 …
P2 pagetable
6 2 3 … P2
28 KB
load 0x0000 PTBR load 0x0800 (2KB) load 0x6000 (24KB) load 0x1444 load 0x0808 load 0x2444 load 0x1444 load 0x0008
SLIDE 20
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
Virtual Physical
PT
P1 pagetable
1 5 4 …
P2 pagetable
6 2 3 … P2
28 KB
load 0x0000 PTBR load 0x0800 (2KB) load 0x6000 (24KB) load 0x1444 load 0x0808 load 0x2444 load 0x1444 load 0x0008 load 0x5444
SLIDE 21
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
Virtual Physical
PT
P1 pagetable
1 5 4 …
P2 pagetable
6 2 3 … P2
28 KB
load 0x0000 PTBR load 0x0800 (2KB) load 0x6000 (24KB) load 0x1444 load 0x0808 load 0x2444 load 0x1444 load 0x0008 load 0x5444
1
SLIDE 22
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
Virtual Physical
PT
P1 pagetable
1 5 4 …
P2 pagetable
6 2 3 … P2
28 KB
load 0x0000 PTBR load 0x0800 (2KB) load 0x6000 (24KB) load 0x1444 load 0x0808 load 0x2444 load 0x1444 load 0x0008 load 0x5444
SLIDE 23
Chapter 19: TLBs
SLIDE 24
Outline
What work can we eliminate? Basic strategy. Workloads, systems, metrics. Context switching and security.
SLIDE 25
Paging Advantages
Flexible Addr Space
- don’t need to find contiguous RAM
- doesn’t waste whole data pages (valid bit)
Easy to manage
- fixed size pages
- simple free list for unused pages
- no need to coalesce
SLIDE 26
Paging Problems
Too big Too slow
SLIDE 27
Paging Problems
Too big Too slow [today’s focus]
SLIDE 28
Translation Steps
H/W: for each mem reference:
- 1. extract VPN (virt page num) from VA (virt addr)
- 2. calculate addr of PTE (page table entry)
- 3. fetch PTE
- 4. extract PFN (page frame num)
- 5. build PA (phys addr)
- 6. fetch PA to register
SLIDE 29
Translation Steps
H/W: for each mem reference:
- 1. extract VPN (virt page num) from VA (virt addr)
- 2. calculate addr of PTE (page table entry)
- 3. fetch PTE
- 4. extract PFN (page frame num)
- 5. build PA (phys addr)
- 6. fetch PA to register
Which steps are expensive?
SLIDE 30
Translation Steps
H/W: for each mem reference:
- 1. extract VPN (virt page num) from VA (virt addr)
- 2. calculate addr of PTE (page table entry)
- 3. fetch PTE
- 4. extract PFN (page frame num)
- 5. build PA (phys addr)
- 6. fetch PA to register
Which steps are expensive?
(cheap) (cheap) (cheap) (cheap) (expensive) (expensive)
SLIDE 31
Translation Steps
H/W: for each mem reference:
- 1. extract VPN (virt page num) from VA (virt addr)
- 2. calculate addr of PTE (page table entry)
- 3. fetch PTE
- 4. extract PFN (page frame num)
- 5. build PA (phys addr)
- 6. fetch PA to register
Which expensive step can we avoid?
(cheap) (cheap) (cheap) (cheap) (expensive) (expensive)
SLIDE 32
Array Iterator
int sum = 0; for (i=0; i<N; i++) { sum += a[i]; }
SLIDE 33
Array Iterator
load 0x3000 load 0x3004 load 0x3008 load 0x300C …
Virt
SLIDE 34
Array Iterator
load 0x3000 load 0x3004 load 0x3008 load 0x300C … load 0x100C load 0x7000 load 0x100C load 0x7004 load 0x100C load 0x7008 load 0x100C load 0x700C
Virt Phys
SLIDE 35
Array Iterator
load 0x3000 load 0x3004 load 0x3008 load 0x300C … load 0x100C load 0x7000 load 0x100C load 0x7004 load 0x100C load 0x7008 load 0x100C load 0x700C
Virt Phys
SLIDE 36
Array Iterator
load 0x3000 load 0x3004 load 0x3008 load 0x300C … load 0x100C load 0x7000 load 0x100C load 0x7004 load 0x100C load 0x7008 load 0x100C load 0x700C
Virt Phys
SLIDE 37
Array Iterator
load 0x3000 load 0x3004 load 0x3008 load 0x300C … load 0x100C load 0x7000 load 0x100C load 0x7004 load 0x100C load 0x7008 load 0x100C load 0x700C
Virt Phys
SLIDE 38
Outline
What work can we eliminate? Basic strategy. Workloads, systems, metrics. Context switching and security.
SLIDE 39
Strategy
Take advantage of repetition. Use a CPU cache.
SLIDE 40
Strategy
Take advantage of repetition. Use a CPU cache.
CPU RAM
memory interconnect
SLIDE 41
Strategy
Take advantage of repetition. Use a CPU cache.
CPU RAM
memory interconnect
PT
SLIDE 42
Strategy
Take advantage of repetition. Use a CPU cache.
CPU RAM
memory interconnect
PT
SLIDE 43
Strategy
Take advantage of repetition. Use a CPU cache.
CPU RAM
memory interconnect
PT
popular PTEs often transferred
SLIDE 44
Strategy
CPU RAM
memory interconnect
PT
Take advantage of repetition. Use a CPU cache.
SLIDE 45
Strategy
Name? ATC: Address Translation Cache? [OSTEP]
CPU RAM
memory interconnect
PT ATC
SLIDE 46
Strategy
Name? ATC: Address Translation Cache? [OSTEP]
- Nope. TLB: Translation Lookaside Buffer
CPU RAM
memory interconnect
PT TLB
SLIDE 47
Name? ATC: Address Translation Cache? [OSTEP]
- Nope. TLB: Translation Lookaside Buffer
CPU RAM ATC
Strategy
SLIDE 48
Name? ATC: Address Translation Cache? [OSTEP]
- Nope. TLB: Translation Lookaside Buffer
CPU RAM Air Traffic Controller
Strategy
SLIDE 49
Strategy
Name? ATC: Address Translation Cache? [OSTEP]
- Nope. TLB: Translation Lookaside Buffer
CPU RAM
memory interconnect
PT TLB
SLIDE 50
Cache Types (more in CS 552)
Direct-Mapped: only one place to put entries Four-Way Set Associative: 4 options Fully-Associative: entries can go anywhere
SLIDE 51
Cache Types (more in CS 552)
Direct-Mapped: only one place to put entries Four-Way Set Associative: 4 options Fully-Associative: entries can go anywhere
- most common for TLBs
- must store whole key/value in cache
- search all in parallel
SLIDE 52
Array Iterator (w/ TLB)
int sum = 0; for (i=0; i<2048; i++) { sum += a[i]; }
SLIDE 53
Array Iterator
load 0x1000 load 0x1004 load 0x1008 load 0x100C …
Virt
SLIDE 54
Virt Phys load 0x1000 load 0x1004 load 0x1008 load 0x100C …
SLIDE 55
Virt Phys
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
PT
P1 pagetable
1 5 4 … P2
28 KB
load 0x1000 load 0x1004 load 0x1008 load 0x100C …
1 2 3
Valid Virt Phys
CPU’s TLB
PTBR
SLIDE 56
Virt Phys
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
PT
P1 pagetable
1 5 4 … P2
28 KB
load 0x1000 load 0x1004 load 0x1008 load 0x100C …
1 2 3
Valid Virt Phys
CPU’s TLB
PTBR
SLIDE 57
Virt Phys
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
PT
P1 pagetable
1 5 4 … P2
28 KB
load 0x1000 load 0x1004 load 0x1008 load 0x100C … load 0x0004
1 2 3
Valid Virt Phys 1 1 5
CPU’s TLB
PTBR
SLIDE 58
Virt Phys
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
PT
P1 pagetable
1 5 4 … P2
28 KB
load 0x1000 load 0x1004 load 0x1008 load 0x100C … load 0x0004 load 0x5000
1 2 3
CPU’s TLB
PTBR
Valid Virt Phys 1 1 5
SLIDE 59
Virt Phys
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
PT
P1 pagetable
1 5 4 … P2
28 KB
load 0x1000 load 0x1004 load 0x1008 load 0x100C … load 0x0004 load 0x5000
1 2 3
CPU’s TLB
PTBR
Valid Virt Phys 1 1 5
SLIDE 60
Virt Phys
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
PT
P1 pagetable
1 5 4 … P2
28 KB
load 0x1000 load 0x1004 load 0x1008 load 0x100C …
1 2 3
CPU’s TLB
PTBR
Valid Virt Phys 1 1 5
load 0x0004 load 0x5000 (TLB)
SLIDE 61
Virt Phys
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
PT
P1 pagetable
1 5 4 … P2
28 KB
load 0x1000 load 0x1004 load 0x1008 load 0x100C …
1 2 3
CPU’s TLB
PTBR
Valid Virt Phys 1 1 5
load 0x0004 load 0x5000 (TLB) load 0x5004
SLIDE 62
Virt Phys
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
PT
P1 pagetable
1 5 4 … P2
28 KB
load 0x1000 load 0x1004 load 0x1008 load 0x100C … load 0x0004 load 0x5000 (TLB) load 0x5004 (TLB) load 0x5008 (TLB) load 0x500C
1 2 3
CPU’s TLB
PTBR
Valid Virt Phys 1 1 5
SLIDE 63
Virt Phys
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
PT
P1 pagetable
1 5 4 … P2
28 KB
load 0x1000 load 0x1004 load 0x1008 load 0x100C … load 0x2000 load 0x0004 load 0x5000 (TLB) load 0x5004 (TLB) load 0x5008 (TLB) load 0x500C
1 2 3
CPU’s TLB
PTBR
Valid Virt Phys 1 1 5
SLIDE 64
Virt Phys
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
PT
P1 pagetable
1 5 4 … P2
28 KB
load 0x1000 load 0x1004 load 0x1008 load 0x100C … load 0x2000 load 0x0004 load 0x5000 (TLB) load 0x5004 (TLB) load 0x5008 (TLB) load 0x500C load 0x0008
1 2 3
CPU’s TLB
PTBR
Valid Virt Phys 1 1 5 1 2 4
SLIDE 65
Virt Phys
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
PT
P1 pagetable
1 5 4 … P2
28 KB
load 0x1000 load 0x1004 load 0x1008 load 0x100C … load 0x2000 load 0x0004 load 0x5000 (TLB) load 0x5004 (TLB) load 0x5008 (TLB) load 0x500C load 0x0008 load 0x4000
1 2 3
CPU’s TLB
PTBR
Valid Virt Phys 1 1 5 1 2 4
SLIDE 66
Virt Phys
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
PT
P1 pagetable
1 5 4 … P2
28 KB
load 0x1000 load 0x1004 load 0x1008 load 0x100C … load 0x2000 load 0x2004 load 0x0004 load 0x5000 (TLB) load 0x5004 (TLB) load 0x5008 (TLB) load 0x500C load 0x0008 load 0x4000
1 2 3
CPU’s TLB
PTBR
Valid Virt Phys 1 1 5 1 2 4
SLIDE 67
Virt Phys
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
PT
P1 pagetable
1 5 4 … P2
28 KB
load 0x1000 load 0x1004 load 0x1008 load 0x100C … load 0x2000 load 0x2004 load 0x0004 load 0x5000 (TLB) load 0x5004 (TLB) load 0x5008 (TLB) load 0x500C load 0x0008 load 0x4000 (TLB)
1 2 3
CPU’s TLB
PTBR
Valid Virt Phys 1 1 5 1 2 4
SLIDE 68
Virt Phys
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
PT
P1 pagetable
1 5 4 … P2
28 KB
load 0x1000 load 0x1004 load 0x1008 load 0x100C … load 0x2000 load 0x2004 load 0x0004 load 0x5000 (TLB) load 0x5004 (TLB) load 0x5008 (TLB) load 0x500C load 0x0008 load 0x4000 (TLB) 0x4004
1 2 3
CPU’s TLB
PTBR
Valid Virt Phys 1 1 5 1 2 4
SLIDE 69
How many TLB lookups?
int sum = 0; for (i=0; i<2048; i++) { sum += a[i]; }
(assume 1KB pages)
SLIDE 70
How many TLB lookups?
int sum = 0; for (i=0; i<2048; i++) { sum += a[i]; }
(assume 1KB pages) 2048/sizeof(int) = 512
SLIDE 71
How many TLB “misses”?
int sum = 0; for (i=0; i<2048; i++) { sum += a[i]; }
(assume 1KB pages)
SLIDE 72
How many TLB “misses”?
int sum = 0; for (i=0; i<2048; i++) { sum += a[i]; }
(assume 1KB pages) if a%4096 is 0, then 2 else 3
SLIDE 73
Miss rate?
int sum = 0; for (i=0; i<2048; i++) { sum += a[i]; }
(assume 1KB pages) 2/512 = 0.4% or 3/512 = 0.6%
SLIDE 74
Hit rate?
int sum = 0; for (i=0; i<2048; i++) { sum += a[i]; }
(assume 1KB pages) 510/512 = 99.6% or 509/512 = 99.4%
SLIDE 75
Outline
What work can we eliminate? Basic strategy. Workloads, systems, metrics. Context switching and security.
SLIDE 76
Reasoning about TLB
Workload: series of loads/stores to accesses TLB: chooses entries to store in CPU Metric: performance (i.e., hit rate) TLB “algebra”, given 2 variables, find the 3rd:
f(W, T) = M
SLIDE 77
Reasoning about TLB
Workload: series of loads/stores to accesses TLB: chooses entries to store in CPU Metric: performance (i.e., hit rate) TLB “algebra”, given 2 variables, find the 3rd:
f(W, T) = M
SLIDE 78
TLB Workloads
Sequential array accesses can almost always hit in the TLB, and so are very fast! What pattern would be slow?
SLIDE 79
TLB Workloads
Sequential array accesses can almost always hit in the TLB, and so are very fast! What pattern would be slow?
- highly random, with no repeat accesses
SLIDE 80
Workload Characteristics
int sum = 0; for (i=0; i<2048; i++) {
- sum += a[i];
}
int sum = 0; srand(1234); for (i=0; i<1000; i++) {
- sum += a[rand() % N];
} srand(1234); for (i=0; i<1000; i++) {
- sum += a[rand() % N];
}
Workload A Workload B
SLIDE 81
time address ? time address ? … …
SLIDE 82
time address Workload A time address Workload B … …
SLIDE 83
time address Workload A time address Workload B … … Spatial Locality Temporal Locality
SLIDE 84
Workload Locality
Spatial Locality: future access will be to nearby addresses Temporal Locality: future access will be repeats to the same data
SLIDE 85
Workload Locality
Spatial Locality: future access will be to nearby addresses Temporal Locality: future access will be repeats to the same data What TLB characteristics are best for each type?
SLIDE 86
A couple policies
LRU: evict least-recently used a TLB slot is needed Random: randomly choose entries to evict When is each better?
SLIDE 87
LRU Troubles
Valid Virt Phys
virtual addresses: 1 2 3 4
SLIDE 88
LRU Troubles
Valid Virt Phys
virtual addresses: 1 2 3 4
SLIDE 89
LRU Troubles
Valid Virt Phys 1 ?
virtual addresses: 1 2 3 4 miss!
SLIDE 90
LRU Troubles
Valid Virt Phys 1 ?
virtual addresses: 1 2 3 4
SLIDE 91
LRU Troubles
Valid Virt Phys 1 ? 1 1 ?
virtual addresses: 1 2 3 4 miss!
SLIDE 92
LRU Troubles
Valid Virt Phys 1 ? 1 1 ?
virtual addresses: 1 2 3 4
SLIDE 93
LRU Troubles
Valid Virt Phys 1 ? 1 1 ? 1 2 ?
virtual addresses: 1 2 3 4 miss!
SLIDE 94
LRU Troubles
Valid Virt Phys 1 ? 1 1 ? 1 2 ?
virtual addresses: 1 2 3 4
SLIDE 95
LRU Troubles
Valid Virt Phys 1 ? 1 1 ? 1 2 ? 3 ?
virtual addresses: 1 2 3 4 miss!
SLIDE 96
LRU Troubles
Valid Virt Phys 1 ? 1 1 ? 1 2 ? 3 ?
virtual addresses: 1 2 3 4
SLIDE 97
LRU Troubles
Valid Virt Phys 1 4 ? 1 1 ? 1 2 ? 3 ?
virtual addresses: 1 2 3 4 miss!
SLIDE 98
LRU Troubles
Valid Virt Phys 1 4 ? 1 1 ? 1 2 ? 3 ?
virtual addresses: 1 2 3 4
SLIDE 99
LRU Troubles
Valid Virt Phys 1 4 ? 1 ? 1 2 ? 3 ?
virtual addresses: 1 2 3 4 miss!
SLIDE 100
LRU Troubles
Valid Virt Phys 1 4 ? 1 ? 1 2 ? 3 ?
virtual addresses: 1 2 3 4
SLIDE 101
LRU Troubles
Valid Virt Phys 1 4 ? 1 ? 1 1 ? 3 ?
virtual addresses: 1 2 3 4 miss!
SLIDE 102
LRU Troubles
Valid Virt Phys 1 4 ? 1 ? 1 1 ? 3 ?
virtual addresses: 1 2 3 4
SLIDE 103
LRU Troubles
Valid Virt Phys 1 4 ? 1 ? 1 1 ? 2 ?
virtual addresses: 1 2 3 4 miss!
SLIDE 104
A couple policies
LRU: evict least-recently used a TLB slot is needed Random: randomly choose entries to evict When is each better? Sometimes random is better than a “smart” policy!
SLIDE 105
Outline
What work can we eliminate? Basic strategy. Workloads, systems, metrics. Context switching and security.
SLIDE 106
Context Switches
What happens if a process uses the cached TLB entries from another process?
SLIDE 107
Context Switches
What happens if a process uses the cached TLB entries from another process? Solutions?
SLIDE 108
Context Switches
What happens if a process uses the cached TLB entries from another process? Solutions?
- flush TLB on each switch
- remember which entries are for each process
SLIDE 109
Address Space Identifier
Tag each TLB entry with an 8-bit ASID
- how many ASIDs to we get?
- why not use PIDs?
- what if there are more PIDs than ASIDs?
SLIDE 110
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
Virtual Physical
PT
P1 pagetable (ASID 11)
1 5 4 …
P2 pagetable (ASID 12)
6 2 3 … P2
28 KB
PTBR
Valid Virt Phys ASID 1 9 11 1 1 5 11 1 1 2 12 1 1 11
TLB:
SLIDE 111
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
Virtual Physical
PT
P1 pagetable (ASID 11)
1 5 4 …
P2 pagetable (ASID 12)
6 2 3 … P2
28 KB
PTBR load 0x1444
Valid Virt Phys ASID 1 9 11 1 1 5 11 1 1 2 12 1 1 11
TLB:
SLIDE 112
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
Virtual Physical
PT
P2
28 KB
PTBR load 0x1444 load 0x2444
P1 pagetable (ASID 11)
1 5 4 …
P2 pagetable (ASID 12)
6 2 3 …
Valid Virt Phys ASID 1 9 11 1 1 5 11 1 1 2 12 1 1 11
TLB:
SLIDE 113
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
Virtual Physical
PT
P2
28 KB
PTBR load 0x1444 load 0x2444
P1 pagetable (ASID 11)
1 5 4 …
P2 pagetable (ASID 12)
6 2 3 …
Valid Virt Phys ASID 1 9 11 1 1 5 11 1 1 2 12 1 1 11
TLB:
SLIDE 114
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
Virtual Physical
PT
P2
28 KB
PTBR load 0x1444 load 0x2444
P1 pagetable (ASID 11)
1 5 4 …
P2 pagetable (ASID 12)
6 2 3 …
Valid Virt Phys ASID 1 9 11 1 1 5 11 1 1 2 12 1 1 11
TLB:
SLIDE 115
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
Virtual Physical
PT
P2
28 KB
PTBR load 0x1444 load 0x2444 load 0x1444
P1 pagetable (ASID 11)
1 5 4 …
P2 pagetable (ASID 12)
6 2 3 …
Valid Virt Phys ASID 1 9 11 1 1 5 11 1 1 2 12 1 1 11
TLB:
SLIDE 116
P1 P2 P2 P1
PT
P1
16 KB 20 KB 24 KB 8 KB 12 KB 4 KB 0 KB
Virtual Physical
PT
P2
28 KB
PTBR load 0x1444 load 0x2444 load 0x1444 load 0x5444
P1 pagetable (ASID 11)
1 5 4 …
P2 pagetable (ASID 12)
6 2 3 …
Valid Virt Phys ASID 1 9 11 1 1 5 11 1 1 2 12 1 1 11
TLB:
SLIDE 117
Address Space Identifier
Context switches are expensive. Even with ASID, other processes “pollute” the TLB.
SLIDE 118
Who changes the TLB?
H/W or OS?
SLIDE 119
Who changes the TLB?
H/W or OS? H/W: CPU must know where pagetables are
- CR3 on x86
- pagetable structure not flexible
- “walk” the pagetable
OS: CPU traps into OS upon TLB miss
- how to avoid double traps?
- more modern
SLIDE 120
Security
Modifying TLB entries is privileged
- otherwise what could you do?
Need same protection bits in TLB as pagetable
- rwx
SLIDE 121
Measurement Demo
(if enough time)