3D TECHNOLOGY FOR IMAGING SENSOR AT CEA-LETI Gabriel Pars April 2015 - PowerPoint PPT Presentation

3D TECHNOLOGY FOR IMAGING SENSOR AT CEA-LETI Gabriel Parès April 2015 | LAL presentation LETI CONFIDENTIAL G. Parès / CEA-Leti

AGENDA • Leti brief overview • Post-processing Leti 3D technology modules state of the art & development  Chip’s Interconnections : micro -bumps/pillars  Chip intra-connections: TSV • 3D examples: imaging sensor application  Image sensor for visible  Image sensor for high energy particles • Conclusion LETI CONFIDENTIAL 3D for imaging sensors | Gabriel Parès April 2015 | 2

LETI AT A GLANCE Photonic Embedded Micro & Nanocharacterisation Chemical & Bio medical plateform systems Nanoelectronic platform material plateform platform platform LETI CONFIDENTIAL 3D for imaging sensors | Gabriel Parès April 2015 | 3

Imaging @ LETI – a global offer From material to system Image processing  from photon to decision System Characterization Component Optics Integration - packaging Modeling - simulation ROIC design Continuous Technologies transfer Detection materials LETI CONFIDENTIAL 3D for imaging sensors | Gabriel Parès April 2015 | 4

WHY DO WE NEED 3D INTEGRATION ?  To solve the following issues :  Form factor decrease :  X & Y axis  Z axis  Performances improvement  Decrease R, C, signal delay  Increase device bandwidth  Decrease power consumption  Heterogeneous integration  Integration of heterogeneous components in the same system  Cost decrease Interposer / substrate Interposer / substrate passives passives Memory Memory  Si surface decrease Logic Logic  Reuse of existing Packaging, BEOL & FEOL lines LETI CONFIDENTIAL 3D for imaging sensors | Gabriel Parès April 2015 | 5

3D TECHNOLOGICAL MODULES OVERVIEW 3D Technological modules : • • Through Silicon via (TSV) Wafer bonding: temporary or permanent • • Redistribution layer (RDL) Wafer thinning • • Under Bump Metallization (UBM) Components stacking • • 3D Interconnections: µbump/µpillar Wafer level packaging Top dies Micro-bumps Front side UBM Micro pillars TSV Passivation RDL Bumps Back side UBM BGA or package LETI CONFIDENTIAL 3D for imaging sensors | Gabriel Parès April 2015 | 6

THE 3D INTERCONNECTIONS DIVA Top Die µbumps/µpillars Top chip TSV & RDL Post ECD Cu/SnAg Post Reflow Bottom chip Die to Die µBumps (  20µm) 6x55 µm 10x80 µm TSV Middle bumps/pillars Board Bottom Die Heterogeneous 3D integration on interposer Post ECD Ni/Au Die to Die µPillars (  20µm) TSV Last From C. Ribière CEA-Leti 2015 ALPS DIVA Post ECD Cu/SnAg Post Reflow Back side : RDL Front side : Damascene Back side material and Die to Substrate Bumps (  55µm) Intradie interconnexions: RDL and TSV stress management LETI CONFIDENTIAL 3D for imaging sensors | Gabriel Parès April 2015 | 7

THE GENERIC TOOLBOX FOR 3D Handling Connecting Die to Substrate TSV Die Placement WL Molding thinning Thick Polymer High throuput handling Solder balls Wire Bonding TSV First molding P&P TSV Middle Temp Bonding Thin Polymer High precision Copper Pillars Solder balls AR10 (Zonebond) molding P&P TSV Last Thin Oxide High temp. Self Assembly Via belt Copper pillar AR2.5 planarization bonding TSV Last Permanent Wafer WLUF µtubes AR5 bonding To Wafer TSV Last Capillary Thinning Cu-Cu High temp Underfill Super TSV Last Rdl Thick Cu High density thinning LETI CONFIDENTIAL 3D for imaging sensors | Gabriel Parès April 2015 | 8

THE DIE-TO-DIE VERTICAL INTER- CONNECTIONS: MICRO-BUMP/MICRO PILLARS/UBM

LETI CONFIDENTIAL 3D for imaging sensors | Gabriel Parès April 2015 | 10

STANDARD FLIP CHIP STACKING OPTIONS Solder balls with UBM on both dies Example : UBM Ti/Ni/Au (PVD/ECD) or Ni/Pd/Au (eless) Medipix Solder balls (Pb, Pb free) UBM Ti/Ni/Au (PVD/ECD) or Ni/Pd/Au (eless) Usual pitch limited to 140 µm (70/70) feasibility proven ~ 70 µm (omegapix) µbump and UBM, usually µbump are on top chips Example : Micro-bumps Cu/SnAg ECD FEI4/sensor UBM Ti/Ni/Au (PVD/ECD) or Ni/Pd/Au (eless) Usual pitch limited to 40 µm (20/20) feasibility proven ~ 20 µm µbump and µpillar (or Cu post), usually µbump are on top chips CMOS/CMOS Micro-bumps Cu/SnAg ECD Micro pillars Cu only or wit cap option (Ni, SnAg or Ti/Au) Usual pitch limited to 40 µm (20/20) feasibility proven ~ 20 µm LETI CONFIDENTIAL 3D for imaging sensors | Gabriel Parès April 2015 | 11

MICRO-BUMPS PORTFOLIO VS CMOS NODES Micro-bumps DRM & schematic Micro-bumps Solder alloy  Wafer size : 300 - 200 mm Cu post  Micro-bumps material : Cu post / SnAg 305 solder Top passivation  Minimum pitch : 40 µm Top metal  Minimum micro-bumps diameter : 20 µm  Micro-bumps thickness (typical): Cu 10µm / SnAg 10µm Micro-bumps Morphological illustrations Micro-bumps on C65 Micro-bumps on FDSOI28 Micro-bumps before reflow Micro-bumps after reflow D= 25 µm D= 18 µm leti leti leti leti leti leti leti leti LETI CONFIDENTIAL 3D for imaging sensors | Gabriel Parès April 2015 | 12

PROCESS OF THE SOLDER BUMPS Semi-additive electroplating growth: • Full sheet seed PVD deposition Ti-Cu Front side CMOS • Photolithography with thick resist (>0 or <0) • Electroplating of the metals: Cu-(Ni)-SnAg- (Au) • Resist stripping • Seed wet/dry etching • Reflow From C. Ribière CEA-Leti 2015 Challenges for fabrication of microbumps << Ø20µm: • New thick resist with better definition • Limitation of the seed layer under-etching • Control of the IMC Cu/SnAg for reliability (mechanical and EMG) LETI CONFIDENTIAL 3D for imaging sensors | Gabriel Parès April 2015 | 13

THE IMC FORMATION DURING REFLOW CYCLE • Copper diffuses inside SnAg • Formation of Cu 6 Sn 5 • Formation of some voids (Kirkendall) at the interface and of Ag 3 Sn precipitates : can lead to reliability issue Présence de voids From C. Ribière CEA-Leti 2015 LETI CONFIDENTIAL 3D for imaging sensors | Gabriel Parès April 2015 | 14

EFFECT OF X REFLOWS • Growth of IMC CU 6 Sn 5 and creation of Cu 3 Sn phase. • Increase of Kirkendall voids at Cu 3 Sn interface Reflow 1X Reflow 3X Reflow 5X From C. Ribière CEA-Leti 2015 LETI CONFIDENTIAL 3D for imaging sensors | Gabriel Parès April 2015 | 15

THE EFFECT OF NI INTERLAYER • Only Ni 3 Sn 4 IMC with slow reaction. • No Kirkendall voids. • But Ni 3 Sn 4 IMC is more fragile // Cu 6 Sn 5 (literature) : impact on reliability needs to be more studied for small diameters SnAg Ni3Sn4 Ni Ni Cu Depotion ECD Cu/Ni/SnAg From C. Ribière CEA-Leti 2015 LETI CONFIDENTIAL 3D for imaging sensors | Gabriel Parès April 2015 | 16

FINE PITCH µBUMPS DEVELOPMENT From C. Ribière CEA-Leti 2015 LETI CONFIDENTIAL 3D for imaging sensors | Gabriel Parès April 2015 | 17

TECHNOLOGY FOR VERY LOW PITCH … INTERCONNECTION High volume manufacturability Advanced (HVM) (300mm compatibility, high technologies speed P&P) TLP(Cu/Sn) Cu pillars Pre-applied underfill Si Si Cu Cu Room T Insertion SiO 2 SiO 2 Si Si Solder-free µinserts Direct bonding WtW or DtW Nickel Micro-insertion Current technologies µtubes Microinsertion 100-30 µm range 30-5 µm range Down to 1µm LETI CONFIDENTIAL 3D for imaging sensors | Gabriel Parès March 2015 | 18

FINE PITCH INTERCONNECTION WITH µTUBES LETI CONFIDENTIAL 3D for imaging sensors | Gabriel Parès April 2015 | 19

FINE PITCH INTERCONNECTION WITH INDIUM BUMPS LETI CONFIDENTIAL 3D for imaging sensors | Gabriel Parès April 2015 | 20

DIRECT BONDING FOR ULTRA LOW PITCH INTERCONNECTION Si Si Cu Cu SiO 2 SiO 2 Si Si Direct bonding transmission electron SEM of bonded patterned WtW or DtW imaging of the copper structure (hybrid oxide- Composite Cu/SiO2 interface pad bonding metal) at 400°C Perfect ohmic contact: 22.5m  .µm2 14µm pitch (Equivalent to bulk copper) along x Measured resistance of 29422 interconnect 7µm along y daisy chain:  88.5% yield, 1,2% standard deviation  Roadmap to Pitch lower than 2 µm, In Progress Min (Ω) Max (Ω) Post bonding annealing Average Standard resistance (Ω) deviation (%) DC5 400°C for 2h 2162 2291 2202 1.18 Source: “200 °C direct bonding copper interconnects : Electrical results and reliability”, L. Di Cioccio et al, IEDM 2011 LETI CONFIDENTIAL 3D for imaging sensors | Gabriel Parès April 2015 | 21

LETI CONFIDENTIAL 3D for imaging sensors | Gabriel Parès April 2015 | 22

UNDERFILL Underfill = material filling the gap created by interconnections between two parts (chip or substrate) Used for different purposes: • physical barrier to moisture to avoid corrosion • filling the air gap around the interconnections before overmolding • lowering strains and stresses in the interconnections when subjected to thermo-mechanical fatigue underfill Si chips underfill underfill Si interposer BGA underfill Source: Yole Développement LETI CONFIDENTIAL 3D for imaging sensors | Gabriel Parès April 2015 | 23

UNDERFILLING TECHNIQUES DEVELOPMENT Post-applied underfill Pre-applied underfills CUF NCP WLUF = NCF Limited for fine pitch Source: A. Garnier, ECTC 2014 Cons: Pro: • • Low througput High density/fine pitch • • Underfill entrapment Narrow stand off • • Process sensitive to No flux interco layout LETI CONFIDENTIAL 3D for imaging sensors | Gabriel Parès April 2015 | 24