Yong-Bin Kim Professor and Director of High Performance VLSI design - - PowerPoint PPT Presentation

Professor and Director of High Performance VLSI design Lab Department of Electrical and Computer Engineering Northeastern University Boston, MA ybk@ece.neu.edu, 617-373-2919 Yong-Bin Kim

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• Prof. Yong-Bin Kim (ECE Dept)
• ETRI: VTR Analog Color Processor Chip,

PCM Codec/Filter Chip

• Intel: Mixed Mode ASIC Design, Pentium Pro

CPU FDIV/MUL Design

• HP: PA RISC CPU O-O-O Control Block Full

Custom Design

• Sun Micro Systems: 1.5 GHz Ultra Sparc CPU

Design Methodology Development

• Prof. Kim’s Background

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HPVLSI Lab. at ECE Dept.

– 17 PH.D amd 30+ MS Students Graduated – Currently 4 PH.D and 3 Master Students working

• n Low Power Integrated Circuit Design,

Nanoscale Integrated Circuit Design Techniques and Methodology – Full Spectrum of CAD Tools including Cadence, Hspice, Synopsys, Covering the Complete Phase & VLSI Design.

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Project Summaries

Current Project Summary

• Semi-Self Calibration of High Speed Transceiver Impedance

Matching for Interface Between DRAM and Soc

• Accurate and Efficient On-Chip Spectral Analysis for Built-In Self Test
• f Low Noise Analog Integrated Circuits
• Low Power Biomimetic Robot Controller Integrated Circuits Design

(CMOS Neuron and Synapse Design)

• PMU (DC-DC Converter) Design for SoC
• Innovative VLSI Circuits and Systems-on-Chip (SoC)
• Nano-Electronics for CMOS and Emerging Technilogies

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Selected Thesis Topics (PH.D Only)

• VLSI Systems Design Based on Wave

Pipelined Circuits (SUN/AMD, Samsung)

• Low Power Digital Adaptive Voltage Scaling

(AVS) Design Based on Hybrid Cotrol and Reverse Phase Mode (Intel, Analog Device)

• An Adaptive Analog Controller VLSI

Design for Biomimetic Robot (Start-Up)

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Selected Thesis Topic(Cont’d)

• Set-Based Circuit Simulation and Design

Using HSPICE (Oracle)

• A CMOS 4Gbps Serial Link Transciever

Design Based on PWAM (Broadcom)

• PVT Variation Aware Power Reduction

Techniques for Nanoscale CMOS Design (Samsung)

• CMOS Low Power All Digital PLL Design

(Marvell)

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Selected Thesis Topic(Cont’d)

• Analysis and Design of Robust SRAM in

Nanometric Circuits (Apple)

• Fully Integrated On-Chip Switched

Capacitor DC-DC Converters (Samsung)

• Self Calibration Method for Mixed Signal

Circuits in Systems-On-Chip (LG)

• Self Calibration of High Speed Transceiver for

DRAM Interface (SK Hynix)

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Low Power Integrated Circuit Design Samples

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Low Power Integrated Circuit Design Samples (Cont’d)

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Low Power Integrated Circuit Design Samples (Cont’d)

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