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Technische Universität München
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White-box Current Source Modeling Including Parameter Variation and - - PowerPoint PPT Presentation
White-box Current Source Modeling Including Parameter Variation and - - PowerPoint PPT Presentation
Technische Universitt Mnchen White-box Current Source Modeling Including Parameter Variation and its Application to Timing Simulation Christoph Knoth, Petra Nordholz Irina Eichwald, Ulf Schlichtmann Technische Universitt Mnchen
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Challenges in Timing Verification
resistive interconnects resistive interconnects coupling noise coupling noise nonlinear input cap nonlinear input cap “arbitrary” signals “arbitrary” signals
Current Source Cell Models support all this! Current Source Cell Models support all this!
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SUBCKT
with linear, nonlinear, static, dynamic components
CSM
few simple devices
CSM – Waveform and Load Independent Cell Model
Driving Cell Arbitrary Load
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Applications
- Timing Verification for arbitrary waveforms
– Resistive Interconnects
- Statistical Timing Analysis with variational waveforms
– [Zolotov, “Compact modeling of variational waveforms”, ICCAD07]
- Noise Analysis
– [Gandikota, “Worst-case aggressor-victim alignment with current source driver models”, DAC09]
- Reduce (Fast)SPICE simulation time
– [This presentation]
V time
Requirements
- Accurate, parametric CSM
- Quick model generation
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Outline
Current Source Model and Problem formulation White-box characterization flow Nominal Parameterized CSM implementation and Results Summary
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White-box Characterization Flow
Logic Cell Transistor Netlist (SUBCKT)
Parameter File
SPICE Topology Analysis Physical Reasoning More Information CSM
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CSM
Current Source Model with Physical Meaning
parasitic delay
- DC port currents
- port charges
- lowpass filter
(only large gates)
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DC-Transfer Characteristic
Automaticcaly derived from netlist Automaticcaly derived from netlist DC simulation DC simulation
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Additional Dynamic Port Current
Automatically derived from netlist Automatically derived from netlist DC simulation DC simulation
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Voltage Approximation Error for Large Inverter (input)
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Typical Lookup Tables for Model Components
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Obtaining Parameterized Models - Linear Sensitivity
The applicability crucially depends on the costs for the sensitivity. The applicability crucially depends on the costs for the sensitivity.
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Obtaining Parameterized Models - Implementation
- Usually transistor quantities cannot be sensed
- Finite Difference always possible
– Nominal Parameter Values – Deflect statistical Parameter – Rerun DC SPICE simulation
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Sensitivity Lookup Tables
Sensitivity of output current w.r.t. oxid thickness
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Outline
Current Source Model and Problem formulation White-box characterization flow Nominal Parameterized CSM implementation and Results Summary
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Simulator
Usage in Existing Simulators
Characterization lookup tables CMI* .spi *Compiled Model Interface .v VerilogAMS module
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CSM Implementation for SPICE Simulators
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Testing Delay and Slope of Individual Gates
- 50 run with arbitrary parameter vector
- 7 process parameters and Vdd-Drop (up to 15%)
- different slope, different loads
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Performance Gains of SPICE and FastSPICE Simulators
c1355
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Summary
- White-box Current Source Model Generation
– Components with physical meaning – Derived from netlist elements (not just port matching) – efficiency is crucial for parametric models
- Parametric Models
– Linear Sensitivities – Available for commercial Spice and FastSPICE simulators – Support VDD-Drop and parameter variation – Reduction of Monte Carlo Simulation times:
- SPICE typically 50-80x
- FastSPICE typically 4-9x
Thank you for your attention.
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BACKUP
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Simulator
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Basic Tasks in Circuit Simulation
Jacobian Matrix Residuum Solution Vector
Simulator Kernel
Linear Solver Simulation Control
Compiled Model
Jacobian Update Residuum Update Numerical Integration
L
- a
d i n g S
- l
v i n g
Newton Raphson
) ( ) ( x F x x J − = Δ ⋅
x x x
n n
Δ + =
+1
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Voltage Approximation Error for large Inverter (Input)
Voltage Approx. Error (Layer 1) Voltage Approx. Error (Layer 7)
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Voltage Approx. Error (Layer 1)
Voltage Approximation Error for large Inverter (Output)
Voltage Approx. Error (Layer 5)
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Model Generation (Cells with multiple stages)
VN Idc,N1 QN1
Qin Vin
Vout Idc,out Qout
QN2