VLSI Testing Introduction Virendra Singh Associate Professor - - PowerPoint PPT Presentation

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VLSI Testing Introduction Virendra Singh Associate Professor - - PowerPoint PPT Presentation

Jan 06, 2023 244 likes •496 views

VLSI Testing Introduction Virendra Singh Associate Professor Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay http://www.ee.iitb.ac.in/~viren/ E-mail:

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VLSI Testing

Introduction

Virendra Singh

Associate Professor Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay

http://www.ee.iitb.ac.in/~viren/ E-mail: viren@ee.iitb.ac.in

Testing & Verification of VLSI Circuits

Lecture 3

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Introduction

  • Many integrated circuits contain fabrication

defects upon manufacture

  • Only 20-60% for high end circuits

manufactured may be defect free

  • ICs must be carefully tested to screen out

faulty parts before integration in systems

  • Latent faults that cause early life failure must

also be screened out through “burn-in” stress tests

21 Jan 2013

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VLSI Realization Process

Determine requirements Write specifications Design synthesis and Verification Fabrication Manufacturing test Chips to customer Customer’s need Test development

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Contract between a design house and a fab vendor

  • Design is complete and checked (verified)
  • Fab vendor: How will you test it?
  • Design house: I have checked it and …
  • Fab vendor: But, how would you test it?
  • Desing house: Why is that important? It is

between I and my clients – it is none of your business

  • Fab vendor – Sorry you can take your

business some where else. complete the story and determine the reasons for the importance of test generation etc.

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Contract between design …

Hence:

  • “Test” must be comprehensive
  • It must not be “too long”

Issues:

  • Model possible defects in the process

– Understand the process

  • Develop logic simulator and fault simulator
  • Develop test generator
  • Methods to quantify the test efficiency

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Need for Testing

  • Functionality issue

– Does the circuit (large or small) work?

  • Application issue

– Life critical applications

  • Maintenance issue

– Need to identify failed components

  • Cost of doing business
  • What does testing achieve?

– Discard only the “bad product”? – see next three slides

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Verification vs. Test

Verification

  • Verifies correctness of

design.

  • Performed by simulation,

hardware emulation, or formal methods.

  • Performed once prior to

manufacturing.

  • Responsible for quality of

design.

Test

  • Verifies correctness of

manufactured hardware.

  • Two-part process:
  • 1. Test generation: software

process executed once during design

  • 2. Test application: electrical tests

applied to hardware

  • Test application performed on

every manufactured device.

  • Responsible for quality of devices.

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Problems of Ideal Tests

  • Ideal tests detect all defects produced in

the manufacturing process.

  • Ideal tests pass all functionally good

devices.

  • Very large numbers and varieties of

possible defects need to be tested.

  • Difficult to generate tests for some real
  • defects. Defect-oriented testing is an
  • pen problem.

21 Jan 2013 EE-709@IITB 8

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Real Tests

  • Based on analyzable fault models, which may

not map on real defects.

  • Incomplete coverage of modeled faults due to

high complexity.

  • Some good chips are rejected. The fraction (or

percentage) of such chips is called the yield loss.

  • Some bad chips pass tests. The fraction (or

percentage) of bad chips among all passing chips is called the defect level.

21 Jan 2013 EE-709@IITB 9

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Testing as Filter Process

Fabricated chips Good chips Defective chips Prob(good) = y Prob(bad) = 1- y Prob(pass test) = high Prob(fail test) = high Prob(fail test) = low Prob(pass test) = low Mostly good chips Mostly bad chips Tested chips

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Students Examination

All Students Pass quality Fail quality Prob(PQ) = .75 Prob(FQ) = .25 Prob(P/PQ) = .95 Prob(F/FQ) = .95 Prob(F/PQ) = .05 Prob( P/FQ) = .05 Prob (P) = 0.72 Prob (F) 0.27

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Roles of Testing

 Detection: Determination whether or not the

device under test (DUT) has some fault.

 Diagnosis: Identification of a specific fault that

is present on DUT.

 Device characterization: Determination and

correction of errors in design and/or test procedure.

 Failure mode analysis (FMA): Determination of

manufacturing process errors that may have caused defects on the DUT.

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IC Testing is a Difficult Problem

  • Need 23 = 8 input patterns to

exhaustively test a 3-input NAND

  • 2N tests needed for N-input circuit
  • Many ICs have > 100 inputs
  • Only a very few input combinations

can be applied in practice 2100 = 1.27 x 1030 Applying 1030 tests at 109 per second (1 GHZ) will require 1021 secs = 400 billion centuries!

3-input NAND

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IC Testing in Practice

For high end circuits

  • A few seconds of test time on very expensive

production testers

  • Many thousand test patterns applied
  • Test patterns carefully chosen to detect likely

faults

  • High economic impact
  • test costs are approaching manufacturing costs

Despite the costs, testing is always imperfect!

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How well must we test?

Approximate order of magnitude estimates

  • Number of parts per typical system: 100
  • Acceptable system defect rate: 1% (1 per 100)
  • Therefore, required part reliability

1 defect in 10,000 100 Defects Per Million (100 DPM) Requirement ~100 DPM for commercial ICs ~1000 DPM for ASICs “Zero Defect” target for automotive

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CADSL Assume 2 million ICs manufactured with 50% yield 1 million GOOD >> shipped 1 million BAD >> test escapes cause defective parts to be shipped For 100 BAD parts in 1M shipped (DPM=100) Test must detect 999,900

  • ut of the 1,000,000 BAD

For 100 DPM: Needed Test Coverage = 99.99%

How well must we test?

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DPM and System Failure Probability

Defective Parts per Million parts shipped:

  • ~ 100 DPM (0.01%) for commercial ICs
  • System with 10 ICs => 0.1% Failure Probability
  • System with 100 ICs => 1.0% Failure Probability
  • System with 500 ICs => 5.0% Failure Probability
  • < 10 DPM Automotive Industry

Target : “Zero” defects!

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Classical Yield Models

Two classes of Manufacturing Defects  Gross or area defects  Random Spot Defects In mature well controlled processes, die yield is mostly limited by random spot defects

  • impossible to completely eliminate

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CADSL The simplest defect distribution model for semiconductor wafers assumes that random spot defects are uniformly distributed Die Yield

x x x x x x x x x x x

λ − =e

Yield and Defect Density

λ = Average number of defects per Die

= Defect Density (~ 0.2 - 1.0 per cm2) x Die Area

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CADSL Die Yield

x x x x x x x x x x x

λ − = e

Yield and Defect Density

λ = Average number

  • f defects per Die

= Defect Density x Die Area

  • Yield = 1/e (37%) for λ = 1
  • Defect Density ~ 0.5 defects/sq cm
  • Largest Die are ~ 2 sq cms

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Defect Clustering on Wafers

The Poisson model has been found to consistently underestimate yield This suggests, defects on semiconductor wafers are not uniformly distributed but are clustered

x x x x x x x

 For a given total number of defects on the

wafer, defect clustering results in more die with multiple defects, and therefore more defect free die (higher yield)

x x x

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For Test Coverage: 99.99% (Escapes 100 per million defective)

  • 1 Million Parts @ 10% Yield

0.1 million GOOD >> shipped 0.9 million BAD >> 90 test escapes DPM = 90 /0.1 = 900

  • 1 Million Parts @ 90% Yield

0.9 million GOOD >> shipped 0.1 million BAD >> 10 test escapes DPM = 10/0.9 = 11

DPM depends on Yield

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Testing Large Complex Die

Testing large, complex low yielding die is the biggest challenge

  • Higher DPM even for equally effective (similar

“coverage” ) tests because of lower yields

  • Difficult to achieve high coverage testing for

large complex die

  • DPM increases non linearly with die complexity

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Real Defect Types

Actual manufacturing defects, flaws,

variability etc. can have very complex interactions leading to unpredictable anomalous electrical behavior

  • Permanent or hard faults
  • Difficult to achieve high coverage testing for

large complex die

  • DPM increases quite non-linearly with die

complexity

21 Jan 2013