VLSI Testing Fault Modeling Virendra Singh Associate Professor - PowerPoint PPT Presentation

VLSI Testing Fault Modeling Virendra Singh Associate Professor Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay http://www.ee.iitb.ac.in/~viren/ E-mail: viren@ee.iitb.ac.in Testing & Verification of VLSI Circuits Lecture 6 CADSL

Failure Rate Vs Product Lifetime 27 Jan 2013 EE-709@IITB 2 CADSL

Definitions  Defect: A defect in an electronic system is the unintended difference between the implemented hardware and its intended design  Error: A wrong output signal produced by defective system is called error. An error is an effect whose cause is some defect  Fault: A representation of a defect at the abstracted function level is called a fault 27 Jan 2013 EE-709@IITB 3 CADSL

Why Model Faults?  I/O function tests inadequate for manufacturing (functionality versus component and interconnect testing)  Real defects (often mechanical) too numerous and often not analyzable  A fault model identifies targets for testing  A fault model makes analysis possible  Effectiveness measurable by experiments 27 Jan 2013 EE-709@IITB 4 CADSL

Some Real Defects in Chips  Processing defects  Missing contact windows  Parasitic transistors  Oxide breakdown  . . .  Material defects  Bulk defects (cracks, crystal imperfections)  Surface impurities (ion migration)  . . .  Time-dependent failures  Dielectric breakdown  Electromigration  . . .  Packaging failures  Contact degradation  Seal leaks  . . . Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation - Semiconductor Devices and Circuits, Wiley, 1981. 27 Jan 2013 EE-709@IITB 5 CADSL

Electromigration (a) (b) (c) (a) Open in a line (b) Short between two lines (whisker) (c) Short between lines on different layers (hillock) 27 Jan 2013 EE-709@IITB 6 CADSL

Mapping Physical Defect into Faults 1  Both the defective resistance in bipolar and a the oxide breakdown in oxide between the source and drain of the NMOS transistor form a short failure mode  Both cases are mapped into a stuck-at fault 27 Jan 2013 EE-709@IITB 7 CADSL

Mapping Physical Defect into Faults 2 A A A Z Z Z Poly Metal Diffusion  Physical defect: A missing metal o NMOS is missing the gate  Failure mode: an open  Fault: open  A possible circuit representation is shown 27 Jan 2013 EE-709@IITB 8 CADSL

Mapping Physical Defect into Faults 3 L 1 L 1 L 1 L 1 L 2 L 2 L 2 L 2 ( a ) ( b ) ( a ) ( b ) S t u c k - a t 1 S t u c k - a t 0 S t u c k - a t 1 V d d S t u c k - a t 0 G N D V d d G N D ( c ) ( c ) B r i d g i n g F a u l t B r i d g i n g F a u l t ( d ) ( d ) 27 Jan 2013 EE-709@IITB 9 CADSL

Observed PCB Defects Occurrence frequency (%) Defect classes 51 Shorts 1 Opens 6 Missing components 13 Wrong components 6 Reversed components 8 Bent leads 5 Analog specifications 5 Digital logic 5 Performance (timing) Ref.: J. Bateson, In-Circuit Testing , Van Nostrand Reinhold, 1985. 27 Jan 2013 EE-709@IITB 10 CADSL

Failure Classification IC Failures Mode Duration Incorrect Design Permanant Hard Parameter Degradation Temporaty Soft Transient Intermittent 27 Jan 2013 EE-709@IITB 11 CADSL

Common Fault Models Single stuck-at faults Transistor open and short faults Memory faults PLA faults (stuck-at, cross-point, bridging) Functional faults (processors) Delay faults (transition, path) Analog faults 27 Jan 2013 EE-709@IITB 12 CADSL

Single Stuck-at Fault  Three properties define a single stuck-at fault Only one line is faulty The faulty line is permanently set to 0 or 1 The fault can be at an input or output of a gate  Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults Faulty circuit value Good circuit value j c 0(1) s-a-0 a d 1(0) g h 1 z i 0 1 e b 1 k f Test vector for h s-a-0 fault 27 Jan 2013 EE-709@IITB 13 CADSL

SA Faults 27 Jan 2013 EE-709@IITB 14 CADSL

SA Faults 27 Jan 2013 EE-709@IITB 15 CADSL

Fault Equivalence  Number of fault sites in a Boolean gate circuit = #PI + #gates + # (fanout branches).  Fault equivalence: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2.  If faults f1 and f2 are equivalent then the corresponding faulty functions are identical.  Fault collapsing: All single faults of a logic circuit can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset. 27 Jan 2013 EE-709@IITB 16 CADSL

Equivalence Rules sa0 sa0 sa1 sa1 sa0 sa1 sa0 sa1 WIRE sa0 sa1 sa0 sa1 AND OR sa0 sa1 sa0 sa1 sa0 sa1 NOT sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 NAND NOR sa1 sa0 sa0 sa1 sa0 sa1 sa1 sa0 sa1 FANOUT 27 Jan 2013 EE-709@IITB 17 CADSL

Equivalence Example sa0 sa1 Faults in red sa0 sa1 removed by sa0 sa1 equivalence collapsing sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 20 Collapse ratio = ----- = 0.625 32 27 Jan 2013 EE-709@IITB 18 CADSL

Fault Dominance  If all tests of some fault F1 detect another fault F2, then F2 is said to dominate F1.  Dominance fault collapsing: If fault F2 dominates F1, then F2 is removed from the fault list.  When dominance fault collapsing is used, it is sufficient to consider only the input faults of Boolean gates.  In a tree circuit (without fanouts) PI faults form a dominance collapsed fault set.  If two faults dominate each other then they are equivalent. 27 Jan 2013 EE-709@IITB 19 CADSL

Dominance Example All tests of F2 F1 s-a-1 001 F2 110 010 s-a-1 000 011 101 100 Only test of F1 s-a-1 s-a-1 s-a-1 s-a-0 A dominance collapsed fault set 27 Jan 2013 EE-709@IITB 20 CADSL

Checkpoints  Primary inputs and fanout branches of a combinational circuit are called checkpoints .  Checkpoint theorem: A test set that detects all single (multiple) stuck-at faults on all checkpoints of a combinational circuit, also detects all single (multiple) stuck-at faults in that circuit. Total fault sites = 16 Checkpoints ( ) = 10 27 Jan 2013 EE-709@IITB 21 CADSL

Multiple Stuck-at Faults  A multiple stuck-at fault means that any set of lines is stuck-at some combination of (0,1) values.  The total number of single and multiple stuck-at faults in a circuit with k single fault sites is 3 k -1.  A single fault test can fail to detect the target fault if another fault is also present, however, such masking of one fault by another is rare.  Statistically, single fault tests cover a very large number of multiple faults . 27 Jan 2013 EE-709@IITB 22 CADSL