Vehicle Tracking Syst em 50 nodes on 4 th f loor 5 level ad hoc - - PDF document

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Wireless Sensor Networks

Lecture 8 – CS252

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Sensor Networks: The Vision

• Push connect ivit y out of t he PC and int o t he

real world

• Billions of sensors and act uat ors

EVERYWHERE!!!

• Zero conf igurat ion
• Build everyt hing out of CMOS so t hat each

device costs pennies

• Enable wild new sensing paradigms

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Why Now?

Combination of :

• Breakthroughs in MEMS technology
• Development of low power radio

technologies

• Advances in low
• power embedded

microcontrollers

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Real World Apps…

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Vehicle Tracking

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Cory Energy Monitoring/ Mgmt Syst em

• 50 nodes on 4 th f loor
• 5 level ad hoc net
• 30 sec sampling
• 250K samples to database over 6 weeks

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St ruct ural perf ormance due t o mult i - direct ional ground mot ions (Glaser & CalTech)

Wir ing f or t r adit ional st ruct ural inst rument at ion + t r uckload of equipment Mot e inf rast ruct ure

1 5 1 3 1 4 6 5 ` 1 5 1 1 8 Mote Layout 1 29

Comparison of Results

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Node Localization

“Best Fit”

Calibration Localization

Regression

• Reducing Noise
• Reducing Error
• Results

Regression

Distance RSSI 40 cm 20 cm 80 cm 60 c

m

100 c

m

Error

60 50 cm

Error Error Error Noise Noise

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Sensor Network Algorithms

• Direct ed Dif f usion – Dat a cent ric rout ing

(Est rin, UCLA)

• Sensor Net work Query Processing (Madden,

UCB)

• Dist ribut ed Dat a Aggregat ion
• Localizat ion in sensor net works (UCLA, UW,

USC, UCB)

• Multi- object t racking/ Pursuer Evader (UCB,

NEST)

• Security

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Recipe For Architectural Research

1. Take known workload 2. Analyze perf ormance on current syst ems 3. Form hypothesis on ways of improving “perf ormance” 4. Build new syst em based on hypot hesis 5. Re- analyze same workload on new system 6. Publish results

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Our Approach… .

• 1. Hypothesize about requirements based on potential

applications

• 2. Explore design space based on these requirements
• 3. Develop hardware platf orm f or experimentation
• 4. Build test applications on top of hardware platf orm
• 5. Evaluate perf ormance characteristics of applications
• 6. GOTO step 1 (hopef ully you’ll come up with a better

set of requirements)

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Sensor Node Requirements

• Low Power, Low Power, Low Power…
• Support Multi- hop Wireless Communicat ion
• Self Conf iguring
• Small Physical Size
• Can Reprogram over Net work
• Meet s Research Goals

– Operating system exploration – Enables exploration of algorithm space – I nstrumentation – Network architecture exploration

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First Decision: The central controller

• What will control the device?
• Modern Microcontroller Sidebar

– What ’s inside a microcont roller t oday? – What peripheral equipment do you need t o support one? – How do you program one?

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Major Axes of Microcontroller Diversity

• Flash based vs. SRAM based

– Combinat ion of FLASH and CMOS logic is dif f icult

• I nternal vs. External Memory
• Memory Size
• Digital Only vs. On- chip ADC
• Operating Voltage Range
• Operating Current, Power States and wake- up times
• P

hysical Size

• Support Circuitry Required

– External Clocks, Voltage Ref erences, RAM

• Peripheral Support

– SPI , USART, I 2C, One- wire

• Cycle Counters
• Capture and Analog Compare
• Tool Chain

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Second Decision: Radio Technologies

• Major RF Devices

– Cordless Phones Digit al/ Analog » Single Channel – Cellular Phones » Multi- channel, Base st at ion cont rolled – 802. 11 » “wireless Ethernet” – Bluetooth » Emerging, low- power f requency hopping

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What is in your cell phone?

• Texas I nst rument ’s TCS2500 Chipset

ARM9, 120Mhz + DSP

>> 270.833 kbps

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RFM TR1000 Radio

• 916. 5 Mhz f ixed carrier f requency
• No bit timing provided by radio
• 5 mA RX, 10 mA TX
• Receive signal digitized based on analog thresholds
• Able to operate in OOK (10 kb/ s) or ASK (115 kb/ s)

mode

• 10 Kbps design using programmed I / O
• Design SPI - based circuit to drive radio at f ull speed

– f ull speed on TI MSP, 50 kb/ s on ATMEGA

• I mproved Digitally controlled TX strength DS1804

– 1 f t to 300 f t transmission range, 100 steps

• Receive signal strength detector

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TR 1000 internals

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Why not use f ederation of CPUs?

• Divide App, RF, Storage and Sensing
• Reproduce PC I / O hierarchy
• Dedicated communications processor could greatly

reduce protocol stack overhead and complexity

• Providing physical parallelism would create a partition

between applications and communication protocols

• I solating applications f rom protocols can prove costly

Flexibility is Key to success

Apps CPU Sensing CPU St orage CPU RF CPU St orage Sensors Radio

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Can you do this with a single CPU?

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The RENE architecture

• Atmel AT90LS8535

– 4 Mhz 8- bit CPU – 8KB I nstruction Memory – 512B RAM – 5mA active, 3mA idle, <5uA powered down

• 32 KB EEPROM

– 1- 4 uj/ bit r/ w

• RFM TR1000 radio

– Programmed I / O – 10 kb/ s – OOK

• Network programmable
• 51- pin expansion connector
• GCC based

tool/ programming chain

1.5”x1” form factor

AT90LS8535 Microcontroller TR 1000 Radio Transceiver 32 KB External EEPROM 51-Pin I/O Expansion Connector 8 Analog I/O 8 Programming Lines SPI Bus Coprocessor Transmission Power Control Digital I/O C S252/ Hill Lec 8. 24 2/ 14/ 02

What is the sof tware environment?

• Do I run JI NI ? Java?
• What about a real time OS?
• I P

? Sockets? Threads?

• Why not?

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TinyOS

• OS/ Runt ime model designed t o manage t he

high levels of concurrency required

• Gives up I P, sockets, threads
• Uses state- machine based programming

concept s t o allow f or f ine grained concurrency

• Provides the primitive of low- level message

delivery and dispat ching as building block f or all dist ribut ed algorit hms

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Key Sof tware Requirements

• Capable of f ine grained

concurrency

• Small physical size
• Ef f icient Resource Utilization
• Highly Modular
• Self Conf iguring

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State Machine Programming Model

• System composed of state machines
• Command and event handlers

transition modules f rom one state to another

– Quick, low overhead, non- blocking state transitions

• Many independent modules allowed to

ef f iciently share a single execution cont ext

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Tiny OS Concepts

• Scheduler + Graph of Component s

– constrained two- level scheduling model: threads + events

• Component :

– Commands, – Event Handlers – Frame (storage) – Tasks (concurrency)

• Const rained St orage Model

– f rame per component, shared stack, no heap

• Very lean mult it hreading
• Ef f icient Layering

Messaging Component init Power(mode) TX_packet(buf) TX_pack et_done (success ) RX_pack et_done (buffer)

Internal State

init power(mode) send_m s g (addr, type, data) msg _rec(type, data) msg _sen d_done)

internal thread

Commands Events

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Application = Graph of Components

RFM Radio byte Radio Packet UART Serial Packet ADC Temp photo Active Messages clocks bit byte packet Route map router sensor appln application HW SW

Example: ad hoc, multi-hop routing of photo sensor readings 3450 B code 226 B data Graph of cooperating state machines

• n shared stack

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System Analysis

• Af ter building apps, system is highly

memory constrained

• Communication bandwidth is limited by

CPU overhead at key times. Communication has bursty phases.

• Where did the Energy/ Time go?

– 50% of CPU used when searching f or packets – With 1 packet per second, >90% of energy goes to RX!

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Architectural Challenges

• I mbalance between memory, I / O and CPU

– I ncrease memory (Program and Data) by selecting dif f erent CPU

• Time/ energy spent waiting f or reception

– Solution: Low- power listening sof tware protocols

• Peak CPU usage during transmission

– Solution: Hardware based communication accelerator

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The MI CA architecture

• At mel ATMEGA103

– 4 Mhz 8- bit C P U – 128KB I nstruction Memory – 4KB RAM – 5.5mA active, 1.6mA idle, <1uA powered down

• 4 Mbit f lash (AT45DB041B)

– SP I interf ace – 1- 4 uj/ bit r/ w

• RFM TR1000 radio

– 50 kb/ s – ASK – Communication focused hardware acceleration

• Net work programmable
• 51- pin expansion connect or

– Analog compare + interrupts

• GCC based t ool/ programming chain

Cost-effective power source 2xAA form factor

Atmega103 Microcontroller TR 1000 Radio Transceiver 4Mbit External Flash 51-Pin I/O Expansion Connector 8 Analog I/O 8 Programming Lines SPI Bus Coprocessor Transmission Power Control Power Regulation MAX1678 (3V) DS2401 Unique ID Hardware Accelerators Digital I/O C S252/ Hill Lec 8. 33 2/ 14/ 02 Start Symbol Search Receiving individual bits Start Symbol Detection Synchronization Radio Samples MAC Delay Transmitting encoded bits Start Symbol Transmission Bit Modulations

Transmission Reception

Encoded data received Data Received

…

Encoded data to be Transmitted Data to be Transmitted Encode processing Decode processing Transmit command provides data and starts MAC protocol.

Wireless Communication Phases

… … … … … …

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Radio I nterf ace

• Highly CPU intensive
• CPU limit ed, not RF limit ed in low power

syst ems

• Example implement at ions

– RENE node: » 19,200 bps RF capability » 10,000 bps implementation, 4Mhz Atmel AVR – Chipcon application note example: » 9,600 bps RF capability » Example implementation 1, 200bps with 8x over sampling on 16 Mhz Microchip PI Cmicro (chipcon application note AN008)

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Node Communication Architecture Options

Application Controller RF Transceiver

Direct Device Control Classic Protocol Processor

Application Controller RF Transceiver Protocol Processor Narrow, refined Chip-to-Chip Interface Raw RF Interface

Hybrid Accelerator

Application Controller RF Transceiver Serialization Accelerator Timing Accelerator Memory I/O BUS Hardware Accelerators C S252/ Hill Lec 8. 36 2/ 14/ 02

Accelerator Approach

• Standard I nterrupt based I / O

perf orm start symbol detection

• Timing accelerat or employed t o

capt ure precise t ransmission t iming

– Edge capture perf ormed to +/ - 1/ 4 us

• Timing inf ormat ion f ed int o dat a

serializer

– Exact bit timing perf ormed without using data path – CPU handles data byte- by- byt e

Hybrid Accelerator

Application Controller RF Transceiver Serialization Accelerator Timing Accelerator Memory I/O BUS Hardware Accelerators

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Results f rom accelerator approach

• Bit Clocking Accelerat or

– 50 Kbps transmission rate » 5x over Rene implementation – >8x reduction in peak CPU overhead

• Timing Accelerat or

– Edge captured to +/ - ¼ us » Rene implementation = +/ - 50 us – CPU data path not involved

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Power Optimization Challenge

Scenario:

• 1000 node multi- hop network
• Deployed network should be “dormant”

until RF wake- up signal is heard

• Af ter sleeping f or hours, network

must wake- up with- in 20 seconds Goal:

• Minimize Power consumption

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What are the important characteristics?

• Transmit Power?
• Receive Power consumpt ion of t he radio?
• Clock Skew?
• Radio turn- on time?

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Solutions

• Minimize the time to check f or

“wake- up” message

• “check” time must be greater than

length of wake- up message

• I f data packets are used f or wake up

signal, then “check” time must exceed packet transmission time

• I nstead use long wake- up tone

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Tone- based wake- up protocol

• Each node turns on radio f or 200us

and checks f or RF noise

• I f present, then node continues to

listen to conf irm the tone

• I f not, node goes back to sleep f or 4

seconds

• Resulting duty cycle? . 0002/ 4 =

. 005 %.

• 200us due to wake- up time of the

radio

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Project I deas

• Tos

_sim ++

– RF usage modeling – Cycle- accurate simulation – Nono- joule- accurate simulation

• Tiny applicat ion specif ic VM

– Source program lang – I ntermediate representation – Mobile code story – Communication model

• Analysis of CPU Mult it hreading/ Radical core

architectures

• Federat ed Archit ect ure Alt ernat ive

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Project I deas (2)

• Closed loop system analysis

– Simulation of closed loop systems – I mpact of design decisions on latency

• Channel characterization, Error Correction
• Stable, energy ef f icient, multi- hop communication

implementation

• Scalable Reliable Multicast Analog
• Sensor network specif ic CPU design
• “Passive Vigilance” Circuits
• P
• wer Harvesting
• Correct Architectural Balance (Memory:I / O:CPU)
• Self - diagnosis/ watchdog architecture
• Cryptographic Support
• Alternate Scheduling Models – P

erhaps periodic real- time

• Explore query processing/ content based routing
• Design and build your own X

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Microcontroller Alternatives

• Atmega 163

– same pin out as RENE – 2x memory – Can self - reprogram

• ARM Thumb

– lower power consumpt ion, lower volt age – great er perf ormance – poor integration slow radio

• TI MSP340

– Superior perf ormance – 1/ 10 power consumpt ion – Better integration

No GCC, t ool chain missing Not enough memory Per ipher al suppor t missing