UMBC A B M A L T F O U M B C I M Y O R T 1 (Jan. - PowerPoint PPT Presentation

Systems Design and Programming Arch. of the 80x86 CMPE 310 Basic Architecture Basic components ISA EISA Bus Microprocessor I/O System Memory Memory VESA Bus PCI DRAM Bus 8086 Plotter Printer SRAM through Serial Keyboard Cache Pentium IV Monitor Floppy ROM Tape Hard Drive Flash Scanner Mouse EEPROM DVD CDROM L A N R Y D UMBC A B M A L T F O U M B C I M Y O R T 1 (Jan. 30th, 2002) I E S R C E O V U I N N U T Y 1 6 9 6

Systems Design and Programming Arch. of the 80x86 CMPE 310 Basic Architecture Bus Architecture: Address bus Microprocessor Data bus MWTC MRDC IOWC IORC DRAM Keyboard ROM Printer The Pentium bus architecture is not this simple. We will elaborate on this later. L A N R Y D UMBC A B M A L T F O U M B C I M Y O R T 2 (Jan. 30th, 2002) I E S R C E O V U I N N U T Y 1 6 9 6

Systems Design and Programming Arch. of the 80x86 CMPE 310 Basic Bus Architecture Bus Architecture: Three buses: • Address: If I/O, a value between 0000H and FFFFH is issued. If memory, it depends on the architecture: 20 -bits (8086/8088) 24 -bits (80286/80386SX) 25 -bits (80386SL/SLC/EX) 32 -bits (80386DX/80486/Pentium) 36 -bits (Pentium Pro/II/III) • Data: 8 -bits (8088) 16 -bits (8086/80286/80386SX/SL/SLC/EX) 32 -bits (80386DX/80486/Pentium) 64 -bits (Pentium/Pro/II/III) • Control: Most systems have at least 4 control bus connections (active low). MRDC (Memory ReaD Control), MWRC , IORC (I/O Read Control), IOWC . L A N R Y D UMBC A B M A L T F O U M B C I M Y O R T 3 (Jan. 30th, 2002) I E S R C E O V U I N N U T Y 1 6 9 6

Systems Design and Programming Arch. of the 80x86 CMPE 310 Basic Bus Architecture Bus Standards: ISA (Industry Standard Architecture): 8 MHz 8-bit (8086/8088) 16-bit (80286-Pentium) EISA : 8 MHz 32-bit (older 386 and 486 machines). PCI (Peripheral Component Interconnect): 33 MHz 32-bit or 64-bit (Pentiums) VESA (Video Electronic Standards Association): Runs at processor speed. 32-bit or 64-bit (Pentiums) Only disk and video. Competes with the PCI but is not popular. L A N R Y D UMBC A B M A L T F O U M B C I M Y O R T 4 (Jan. 30th, 2002) I E S R C E O V U I N N U T Y 1 6 9 6

Systems Design and Programming Arch. of the 80x86 CMPE 310 Basic Bus Architecture Bus Standards: USB (Universal Serial Bus): 10 Mbps (extensions to 100Mbps) Newest systems. Serial connection to microprocessor. For keyboards, the mouse, modems and sound cards. To reduce system cost through fewer wires. AGP (Advanced Graphics Port): 66MHz Newest systems. Fast parallel connection: Across 64-bits for 533MB/sec. For video cards. To accommodate the new DVD (Digital Versatile Disk) players. L A N R Y D UMBC A B M A L T F O U M B C I M Y O R T 5 (Jan. 30th, 2002) I E S R C E O V U I N N U T Y 1 6 9 6

Systems Design and Programming Arch. of the 80x86 CMPE 310 Basic Memory Architecture Bank layout High bank Low bank FFFFF FFFFFF FFFFFE FFFFE FFFFFD FFFFFC 8 bits 8 bits 8 bits Odd bytes Even bytes 1 MB 8 MB 8 MB 00002 000005 000004 00001 000003 000002 00000 000001 000000 D7-D0 D15-D8 D7-D0 8086 (1MB only) 8088 80286, 80386SX 80386SL/SLC(32MB) L A N R Y D UMBC A B M A L T F O U M B C I M Y O R T 6 (Jan. 30th, 2002) I E S R C E O V U I N N U T Y 1 6 9 6

Systems Design and Programming Arch. of the 80x86 CMPE 310 Basic Memory Architecture Bank layout Bank 3 Bank 2 Bank 1 Bank 0 FFFFFFFF FFFFFFFE FFFFFFFD FFFFFFFC FFFFFFFB FFFFFFFA FFFFFFF9 FFFFFFF8 8 bits 8 bits 8 bits 8 bits 1 GB 1 GB 1 GB 1 GB 0000000A 00000009 00000008 0000000B 00000007 00000006 00000005 00000004 00000003 00000002 00000001 00000000 D31-D24 D23-D16 D15-D8 D7-D0 80386DX, 80486 L A N R Y D UMBC A B M A L T F O U M B C I M Y O R T 7 (Jan. 30th, 2002) I E S R C E O V U I N N U T Y 1 6 9 6

Systems Design and Programming Arch. of the 80x86 CMPE 310 Basic Memory Architecture Bank layout Bank 7 Bank 6 Bank 5 Bank 4 FFFFFFFF FFFFFFFE FFFFFFFD FFFFFFFC FFFFFFF7 FFFFFFF6 FFFFFFF5 FFFFFFF4 8 bits 8 bits 8 bits 8 bits 512 MB 512 MB 512 MB 512 MB 00000015 00000017 00000016 00000014 0000000F 0000000D 0000000E 0000000C 00000007 00000006 00000005 00000004 D63-D56 D47-D40 D55-D48 D39-D32 Bank 3 Bank 1 Bank 2 Bank 0 FFFFFFFB FFFFFFF9 FFFFFFFA FFFFFFF8 FFFFFFF1 FFFFFFF3 FFFFFFF2 FFFFFFF0 8 bits 8 bits 8 bits 8 bits 512 MB 512 MB 512 MB 512 MB 00000013 00000012 00000011 00000010 0000000B 0000000A 00000009 00000008 00000003 00000002 00000001 00000000 D31-D24 D23-D16 D15-D8 D7-D0 Pentium/Pro/II/III L A N R Y D UMBC A B M A L T F O U M B C I M Y O R T 8 (Jan. 30th, 2002) I E S R C E O V U I N N U T Y 1 6 9 6

Systems Design and Programming Arch. of the 80x86 CMPE 310 Basic I/O Architecture DRAM (Main Memory) Active Processes ISR NIC NIC ISR sound I/O Space Other OS code FFFF Interrupt Vectors 0000 Mem Ports Bus I/O Bus Micro IRQs Sound card INTR processor 0 1 2 ... 7 Ports PIC L A N R Y D UMBC A B M A L T F O U M B C I M Y O R T 9 (Jan. 30th, 2002) I E S R C E O V U I N N U T Y 1 6 9 6

Systems Design and Programming Arch. of the 80x86 CMPE 310 Interrupt Vectors (DOS PC) Address Interrupt # FFFFFH 1FH 7C-7F Video Graphic Chars Pts to Data BIOS Program Area 1EH 78-7B Diskette Parameters 1DH 74-77 Video Initialization 1CH 70-73 Timer Tick (18.2/sec) Read-Only Memory 1BH 6C-6F Keyboard Break 1AH 68-6B Software Interrupts Time of Day 19H 64-67 Bootstrap Synchronous 18H 60-63 Resident BASIC 17H 5C-5F Printer 16H 58-5B Keyboard 15H 54-57 Cassette 14H 50-53 Communications 13H 4C-4F Diskette/Disk 12H 48-4B Memory 11H 44-47 Equipment Check 10H 40-43 Video Hardware Interrupts FH 3C-3F Printer EH 38-3B Diskette Asynchronous DH 34-37 Disk CH 30-33 8259A Communications BH 2C-2F 00500H Communications AH 28-2B Reserved BIOS Data area 64 long words 9H Keyboard 24-27 8H 20-23 Time of Day 00400H 7H 1D-1F Available Int. vectors Reserved 6H 224 long words 18-1B Microprocessor Reserved (DOS int #s 20H-3FH) 5H 14-17 Print Screen 00080H Interrupts 4H 10-13 Overflow (CPU) 32 long words Interrupt Vectors 3H C-F Breakpoint (CPU) 2H 00000H 8-B Non-maskable (8087) 1H 4-7 Single Step (CPU) DRAM (Main Memory) 0-3 0H Divide by zero (CPU) L A N R Y D UMBC A B M A L T F O U M B C I M Y O R T 10 (Jan. 30th, 2002) I E S R C E O V U I N N U T Y 1 6 9 6

Systems Design and Programming Arch. of the 80x86 CMPE 310 I/O Space It is important to notice that these I/O addresses are NOT memory-mapped addresses on the 80x86 machines. I/O Device Space FFFF I/O Expansion Area COM1 03F8 Floppy Disk Controller 03F0 CGA Adapter 03D0 0378 LPT1 Hard Disk Controller 0320 64K 8-bit I/O devices COM2 02F8 8255 (PIA) 0060 Timer (8253) 0040 Interrupt Controller 0020 DMA Controller 0000 Special instructions (IN/OUT) are used to communicate to the I/O devices. L A N R Y D UMBC A B M A L T F O U M B C I M Y O R T 11 (Jan. 30th, 2002) I E S R C E O V U I N N U T Y 1 6 9 6