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Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 1 (November 26, 2000 6:44 pm)

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CMOS Processing Technology Silicon: a semiconductor with resistance between that of conductor and an insulator. Conductivity of silicon can be changed several orders of magnitude by intro- ducing impurity atoms in silicon crystal lattice.

• Impurities that use electrons: acceptors (p-type), e.g., Boron.
• Impurities that provide electrons: donors (n-type), e.g., Phosphorous.

Wafer: 75mm to 230mm (~3” to ~9”) and 0.25mm to 1mm thick. Oxidation: Formation of glass or SiO2. Wet Oxidation uses water vapor and Dry Oxidation uses pure oxygen. SiO2 growth consumes silicon, grows into the substrate. SiO2 is twice the volume of Si, projects above the substrate as well.

Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 2 (November 26, 2000 6:44 pm)

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CMOS Processing Technology Epitaxy, Ion-Implantation and Deposition/Diffusion: Ways of introducing impurities into pure silicon.

• Epitaxy: Single-crystal film grown on silicon surface.
• Deposition: Evaporate dopant material onto surface, high temps drive

impurities into silicon bulk (diffusion).

• Ion implantation: Highly energized donor and acceptor atom driven into

the silicon. How much dopant that is introduced is controlled by energy and amount of time. Where it is introduced is controlled by masks (thin films of special material). Mask materials include: photoresist polysilicon silicon dioxide (SiO2) silicon nitride (SiN)

Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 3 (November 26, 2000 6:44 pm)

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CMOS Processing Technology Selective diffusion: Masks act as a barrier to prevent impurities from diffus- ing. Process involves:

• Patterning windows in the mask on the die surface.
• Introducing impurities in exposed regions.
• Removing the mask.

For example, to cut windows into the glass after oxidation step: Acid resistant coating (photoresist) spread evenly on surface. Silicon Wafer Photoresist SiO2 (Glass)

Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 4 (November 26, 2000 6:44 pm)

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CMOS Processing Technology Polymerized in areas exposed by UV light. Mask controls region exposed. Silicon Wafer Photoresist SiO2 Mask Mask UV light

Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 5 (November 26, 2000 6:44 pm)

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CMOS Processing Technology Organic solvent removes polymerized areas. Windows are etched using an acid and the photoresist is removed. Photoresist SiO2 Silicon Wafer Photoresist SiO2 Silicon Wafer Silicon Wafer SiO2 Photoresist removed

Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 6 (November 26, 2000 6:44 pm)

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CMOS Processing Technology Positive resist: Exposed photoresist removed. Negative resist: Unexposed photoresist removed. UV light defraction and alignment tolerances limit line widths to ~0.8microns. Electron beam lithography: Reduces line width limits to 0.5microns. Adv:

• No intermediate hardware images such as masks.
• Changes to patterns can be implemented immediately.

Disadv:

• Cost of equipment is high.
• Requires large amount of time to process each wafer.

Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 7 (November 26, 2000 6:44 pm)

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CMOS Processing Technology Polysilicon: A polycrystalline (not a single crystal) form of silicon. Used as:

• Interconnection material.
• Gate electrodes.
• *** A mask to allow precise definition of source and drain ***.

Undoped poly has a very high resistance. Poly and the source/drain regions are usually doped at the same time. Silicon Gate Process: Oxidation and etching of the active region: SiO2 - Field Oxide

p-substrate

Active region (isolates active regions from

• ther active regions)

Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 8 (November 26, 2000 6:44 pm)

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CMOS Processing Technology Thin Oxide grown: Polysilicon deposited and etched: Field Oxide

p-substrate

Thinox (10 -> 30nm) Field Oxide

p-substrate

Poly Thinox

Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 9 (November 26, 2000 6:44 pm)

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CMOS Processing Technology Etching of thinox and dopant Ion-Implantation or Deposition/Diffusion: SiO2 and contact cuts. Field Oxide

p-substrate

n+ n+

*** Self-aligned source and drain *** do NOT extend under the gate.

gate

p-substrate

SiO2

n+ n+

Contact cuts

gate

Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 10 (November 26, 2000 6:44 pm)

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CMOS Processing Technology Aluminum evaporated and etched:

p-substrate

Aluminum

n+ n+

contacts

Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 11 (November 26, 2000 6:44 pm)

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CMOS Processing Technology Parasitic MOS transistor: Field device Countermeasures: Make the threshold voltage of field device high by:

• Making the field oxide thick.
• Introducing a “channel-stop” diffusion (higher impurity concentration).

Poly or m etal runner n+ n+ p-substrate n+ n+ U nexpected n-channel transistor Field device

Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 12 (November 26, 2000 6:44 pm)

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CMOS Processing Technology Four main CMOS technologies:

• n-well process
• p-well process
• twin-tub process
• silicon on insulator

Major process steps of n-well process:

• n-well mask used to create n-well or n-tub via ion-implantation or deposi-

tion/diffusion.

p-substrate n-w ell lightly doped n-w ell region for p-transistors

Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 13 (November 26, 2000 6:44 pm)

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CMOS Processing Technology

• active mask defines areas where transistors are fabricated.
• p-well mask used to produce channel-stop (p+ diffusion), field oxide grown.

Silicon N itride (SiN ) Thinox p-substrate n-w ell lightly doped p-substrate n-w ell lightly doped Field oxide C hannel stop

(Complement of n-well mask)

Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 14 (November 26, 2000 6:44 pm)

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CMOS Processing Technology

• poly mask used to etch poly patterns.
• n-plus mask (select mask) used to indicate those thin-oxide areas and poly

that are to implanted n+.

p-substrate n-w ell lightly doped Poly p-substrate n-w ell lightly doped n

+diffusion

O hm ic contacts

areas are also doped in n-w ells for w ell plugs

Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 15 (November 26, 2000 6:44 pm)

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CMOS Processing Technology

• p-plus mask used to indicate those thin-oxide areas and poly that are to

implanted p+.

• Surface is covered with SiO2 and contact cuts made.

p-substrate n-w ell lightly doped p

+diffusion

O hm ic contacts

areas are also doped in p-substrate for w ell plugs

p-substrate n-w ell lightly doped C

• ntact

cuts SiO

2

to diffusion to poly

Principles of VLSI Design CMOS Processing Technology CMSC 491B/711 16 (November 26, 2000 6:44 pm)

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CMOS Processing Technology

• Metallization applied and etched using metal mask.
• The wafer is then passivated and opening to bond pads are etched.

p-substrate n-w ell lightly doped A lum inum