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Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 1 (November 27, 2000 6:34 pm)

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CMOS Logic Structures Full complementary static CMOS gates may be undesirable because:

• The area overhead.
• Their speed may be too slow.
• The function may not be feasible as a full complementary structure (e.g.

PLA). Smaller faster gates can be implemented at the cost of:

• Increased design time.
• Increased operational complexity.
• Decreased operational margin.

Full complementary gates can be designed as ratioless circuits:

• A fixed ratio in size between pull-up and pull-down structures is not

required for proper operation. Unlike those we will consider now.

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 2 (November 27, 2000 6:34 pm)

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CMOS Logic Structures Pseudo-nMOS logic Gain ratio of n-driver transistors to p-transistor load (betadriver/betaload), is important to ensure correct operation. Accomplished by ratioing the n and p transistor sizes. Z = A.(B+C)+(D.E) A B C D E Main problem: Static power dissipation Advantages: Capacitive load on inputs is

• nly one gate unit.

Gain of the pull-up has to be decreased to provide adequate noise margins (when minimum Density advantage over full complementary CMOS. sized transistors are used). Slows rise time.

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 3 (November 27, 2000 6:34 pm)

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CMOS Logic Structures Dynamic CMOS Logic Pull-up time improved by virtue of the active switch (p-transistor can be much larger). Pull-down time increased due to the ground switch. z n-logic block clk inputs Precharge phase: Clk = 0 Evaluate phase: Clk = 1 Input capacitance: Same as that of pseudo-nMOS. Problem: Inputs can only change during the precharge phase. If they change during evaluate, charge redistribution can corrupt output voltage. Simple single phase dynamic CMOS:

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 4 (November 27, 2000 6:34 pm)

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CMOS Logic Structures Dynamic CMOS Logic What is wrong with cascading these structures? (Hint: Consider the delay in the discharge of the left-most n-logic block at the start of the evaluate phase). z n-logic block clk inputs z n-logic block Other inputs

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 5 (November 27, 2000 6:34 pm)

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CMOS Logic Structures CMOS Domino Logic: These structures can be cascaded. In a cascaded set of logic blocks, each stage evaluates and causes the next stage to evaluate (in the same way a line of dominos fall). A B C D E

z

Clk Precharge phase: Output

• f buffer, z, is zero.

Evaluate phase: Output, z, Simple mod of Dynamic logic: Added a static conditionally goes high. Next domino stage. CMOS inverter precharge evaluate Can be made static or latching with the addition of a (weak) p and Dynamic circuit as shown: feedback. Only non-inverting forms of logic possible.

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 6 (November 27, 2000 6:34 pm)

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CMOS Logic Structures Pass-Transistor Logic: P1 A A Boolean P1 P2 P3 P4 A A B B F(A,B) Pass variables Control variables P4 P3 P2 P1 AND(A,B) Operation 1 XOR(A,B) 1 1 NOR(A,B) 1 (Values from registers). Function Unit (Set by opcode).

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 7 (November 27, 2000 6:34 pm)

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CMOS Logic Structures Other forms of CMOS logic include: BiCMOS Logic Clocked CMOS Logic (C2MOS). NP Domino Logic (Zipper CMOS). Cascade Voltage Switch Logic (CVSL). Source Follower Pull-up Logic (SFPL). (See Weste and Eshraghian for details.) Where should one use what gate? Complementary: Best option for most cases. Safe, fast, no DC power. Pseudo-nMOS: Large fan-in NOR gates, i.e. PLAs, ROMs. DC power. Transmission gate: Speed advantage, good for complex boolean functions. CMOS domino logic: Low-power, high speed. Requires simulation!

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 8 (November 27, 2000 6:34 pm)

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Clocked Systems Majority of VLSI systems are Finite State machines and Pipelined machines: Logic Inputs Current Outputs State Bits Next State Bits Q D Combinational D Q Logic inputs Pipelined System D Q Logic D Q clk clk(s)

• utputs

FSM Feedback No feedback

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 9 (November 27, 2000 6:34 pm)

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Clock Strategy One of the most important decisions made at the start of a design is the selec- tion of a clocking strategy. It effects: How many transistors are used per storage element. How many clock signals need to be routed throughout the chip. Topics: Latch, Master-Slave Flip-flop and Edge-Triggered Flip-flop designs. Setup and Hold time and clock race conditions. CMOS Static and Dynamic Flip-flops. Single phase clocking, clock skew/slew. Two-phase clocking techniques. Clock generation techniques.

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 10 (November 27, 2000 6:34 pm)

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Latches and Flip-flops

R S

S R Q Q 1 1 1 1 1 Q NOR Q Q Q 1 version The length of the trigger pulse applied to S or R has to larger than the loop delay of the cross-coupled pair. Note that this mode is forbidden since the constraint Q and Q are not complementary. Also, the return to 00/11 leaves the FF in an unpredictable state.

S R

Q Q S R Q Q 1 1 1 1 1 Q Q 1 1 1 Set-Reset Flip-fl

• p

NAND version Positive logic Negative logic

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 11 (November 27, 2000 6:34 pm)

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Latches and Flip-flops The ambiguity of having a non-allowed mode caused by trigger pulses going active simultaneously can be avoided by adding two feedback lines: Note if both J and K are high, and clock pulses, the output is complemented. However, doing so enables the other input and the FF oscillates. This places some stringent constraints on the clock pulse width (e.g. < than the propagation delay through the FF). Synchronous circuit: Changes in the output logic states of all FFs in a design are synchronized with the clock signal, phi.

S R

Q Q K J φ Jn Kn Qn+1 Qn 1 1 1 1 1 Qn

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 12 (November 27, 2000 6:34 pm)

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Latches and Flip-flops Note that the: T FF (toggle FF) is a special case of the JK with J and K tied together. D FF (delay FF) is a special case with J and K connected with complemen- tary values of the D input. Here the D FF generates a delayed version of the input signal synchro- nized with the clock. These FFs are also called latches. A FF is a latch if the gate is transparent while the clock is high (low). Any changes in the input are refl ected in the output after a nominal delay. The transparent nature can cause race problems: D φ Q Q 1 This circuit oscillates as long as phi remains high. One way to avoid the race is to use the master-slave approach.

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 13 (November 27, 2000 6:34 pm)

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Master-Slave Flip-flops 1 D 1 Q QM Clk Clk Clk D QM Q Latches are transparent on half of the Negative level-sensitive Positive level-sensitive latch latch clock cycle and subject to race conditions.

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 14 (November 27, 2000 6:34 pm)

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Master-Slave Set/Clear Asynchronous FFs Or 1 D 1 Q QM Clk Clk Clr Set Set Clr Clk reset P P set reset Q Q Clk set D

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 15 (November 27, 2000 6:34 pm)

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Edge-triggered FFs Problem with master-slave approach: The circuit is sensitive to changes in the input signals as long as phi is high. If the inputs do not remain constant when the clock is high, the master follows D, which, for example, consumes power. The fix is to allow the state of the FF to change only at the rising (falling) edge

• f the clock.

φ In (1) In (0) Out φ In In Out Results in a short low-going pulse at the output of N2 with length N1 N2 approximately equal to the propagation delay through N1. Pulse (0)

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 16 (November 27, 2000 6:34 pm)

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Edge-triggered FFs The modification applied to the JK FF is shown below. Note that the inputs must be stable for some time before the clock goes low. This is also true for the master-slave D FF, but the constraints are different. Let’s first define some terms.

S R

Q Q K J φ Low-going pulses are generated on S and R with the low going edge

• f the clock.

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 17 (November 27, 2000 6:34 pm)

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Flip-flop Timing Definitions Timing diagram showing the terms used to define the proper operation of a Flip-fl

• p.

Tc: Clock Cycle Time. Ts: The amount of time before the clock edge that the D input has to be stable. Th: Data has to be held for this period while the clock travels to the point of storage. Tq: Clock-to-Q delay: Delay from the positive clock input to the new value of Q. Clock Cycle Time (Tc) Setup time Hold time Th Ts Clock-to-Q delay (Tq) Data (Q is indeterminate in this region)

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 18 (November 27, 2000 6:34 pm)

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Setup/Hold Time Violations Depending on the design, one or both of Ts and Th may have to be non-zero. For example, the master-slave D FF is likely to require a longer setup time than the edge-triggered D FF. Edge triggered FF prevents the "master" from following the D input so the FF’s internal delay does not affect setup time. D QM Q Y X D X Y Clk Let’s assume a 1 is the "correct" storage value. Since setup time is violated, a zero will be "latched" instead. The delay through inverters G1 and G2. "Glitches" in the combo logic. G1 G2 S1 S2 S1 opens and S2 closes.

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 19 (November 27, 2000 6:34 pm)

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Setup/Hold Time Violations The hold time interval starts with the beginning of the clock transition. Clock skew and slew and other design details of the FF affect the hold time. Toggle Flip-Flop with Asynchronous Clear: C Clk QM C C C Used in counters. Clk Clr Out and two NANDs. Can also use NAND SR FF T FF Divides Clk by 2.

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 20 (November 27, 2000 6:34 pm)

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System Timing Two possible strategies to implement clocked systems: Latches are a more economical implementation strategy but are transparent

• n half of the clock cycle, and cannot be used in feedback systems.

Also, the following constraint must be met for latches: Td < Tc/2 - Tq - Ts where Td is the worst case propagation delay, Tc is the clock cycle time, Tq is the Clock-to-Q time of latch A and Ts is the setup time for latch B. Logic inputs clk

• utputs

Combinational Reg A Reg B inputs clk

• utputs

Combinational Latch A Latch B Tq Ts Td Logic Positive level-sensitive latch.

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 21 (November 27, 2000 6:34 pm)

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Clock Race Conditions Occurs when the data input to the register does not obey the setup and hold- time constraints. Delays in the clock line to Reg B (hold-time violation). New data stored instead of previous data: Logic D clk Q’ Combinational Reg A Reg B τ Q D’ Q D’ clk clk’ clk’ clock delayed to Reg B new data previous data new data latched in error

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 22 (November 27, 2000 6:34 pm)

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Clock Race Conditions Delays in the combinational logic that are larger than the clock cycle time (setup violation). Data arrives late at Reg B, old data retained instead of latching new data. As you can see, designers have to walk a temporal ’tight-rope’, e.g., they have to minimize clock skew while considering worst and best case delays through combinational logic. D clk Q’ Reg A Reg B

τ

Q D’ Q D’ clk new data previous data delayed Old data latched in error.

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 23 (November 27, 2000 6:34 pm)

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CMOS Static Flip-Flops Full complementary version of the master-slave FF requires 38 transistors !

S R

SI RI K J φ

S R

Q Q

Alternatively,

φ Q Q

R S

M1 M2 M3 M4 This strategy requires transistor sizes to be taken into account. Assume Q is high and R pulsed. M3 and M4 must "overpower" M2 and reduce Q to < threshold of M5 M6 M5 and M6. an 18 transistor version using

φ

A variation of this, which combines phi and R/S, is the 6 trans. SRAM. this building block:

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 24 (November 27, 2000 6:34 pm)

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CMOS Dynamic Flip-Flops Positive feedback is not the only means to implement a memory function. A capacitor can act as a memory element as well. In this case, a periodic refresh is required (in the millisecond range) due to leak- age (hence the word dynamic). Consider the following "cheaper" (1/2 transmission gate) positive level-sensi- tive latch as a step toward deriving a dynamic FF: φ1 φ1 Out Static as long as φ1 is kept low. When φ1 is high, In is Out In sampled and stored on internal capacitors. A B Logic 1 degraded by Vt.

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 25 (November 27, 2000 6:34 pm)

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CMOS Dynamic Flip-Flops A master-slave FF is created by cascading two of these latches and reversing the clocks. The problem with this latch is that phi1 and phi1 might overlap, which may cause two types of failures: Node A can become undefined as it is driven by both D and B when phi1 and phi1 are both high. D can propagate through both the master and slave if both phi1 and phi1 are high simultaneously for a long enough period. φ1 φ1 QM D φ1 φ1 Q A N1 N2 A B

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 26 (November 27, 2000 6:34 pm)

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Single Phase Clock Skew/Slew Clock skew causes confl icts and transpar ency. Clock slew (slow rise and fall times) can also cause transparency: Clock skew is a dominant problem in current high performance designs. φ1 φ1 Both n transistors are "on". φ1 φ1

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 27 (November 27, 2000 6:34 pm)

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CMOS Dynamic Two-Phase Flip-Flops Pseudostatic FF: The fix is to use two non-overlapping clocks phi1 and phi2: A large tphi-12 allows proper operation even in the presence of clock skew. Note that node A fl

• ats (dynamic) during the time period tphi-12 but is driven

during tphi-1 and tphi-2. Hence, the name pseudostatic. φ2 φ1 QM D φ1 φ2 Q A A φ1 φ2 tφ12 tφ1 tφ2

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 28 (November 27, 2000 6:34 pm)

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CMOS Dynamic Two-Phase Flip-Flops This version is simplier (6 trans) and is often used in pipelined datapaths for microprocessors and signal processors. Disadv: 2 non-overlapping clocks required (4 if transmission gates are used). These implementations MUST be simulated at all process corners (under worst-case conditions). φ1 D φ2 Q Degraded ’1’ values may increase static current if below Vtp. φ1 D φ2 Q VDD VDD p leakers p leakers provide fully restored logic levels.

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 29 (November 27, 2000 6:34 pm)

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Two-Phase Clocking Clock skew/slew: φ1 logic large delay φ1 φ2 logic small delay φ2 Both n-transistors Nonoverlapping clocks: become transparent! Overlap! Slew Skew φ1 φ2 Excessive loads can increase rise/fall times. Non-overlapping at these points

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 30 (November 27, 2000 6:34 pm)

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CMOS Dynamic Two-Phase Flip-Flops C2MOS: A clever method which is insensitive to clock skew: VDD D φ1 φ1 VDD Q φ1 VDD φ1 GND D Q Note: Dual phase version is identical except φ2 and φ2 are used to drive the n/p-trans in the right inverter. φ1 φ1 φ1 φ1

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 31 (November 27, 2000 6:34 pm)

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CMOS Dynamic Two-Phase Flip-Flops C2MOS is insensitive to overlap as long as the rise and fall times of the clk edges (clock slew) are sufficiently small:

VDD

D φ1 φ1

VDD

Q φ1 φ1

VDD

D

VDD

Q

VDD

D

VDD

Q 1-1 overlap. 0-0 overlap. 1 1 No race is possible ! In order for D to race to the Q, a pull-up followed by a pull-down must be enabled.

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 32 (November 27, 2000 6:34 pm)

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C2MOS Flip-Flop Races are just not possible since the overlaps activate either the pull-up or the pull-down networks but never both simultaneously. The inverters force 0-1 and 1-0 propagation modes only. However, if the rise and fall times of the clock are slow, there exists a time slot in which both n- and p-transistors are conducting simultaneously. Correct operation requires the rise/fall times be smaller than about 5 times the propagation delay through the FF. This is not hard to meet in practical designs, making C2MOS especially attractive in high speed designs where avoiding clock overlap is hard. Lots of other possible latch configurations, static and dynamic -- see Weste and Eshraghian.

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 33 (November 27, 2000 6:34 pm)

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Single Phase Local Clock Generation Clock skew is minimized but area cost is severe. QM φ φ φ φ φ φ D Q Q Clk φ φ Local clock generation: Cost is extra area taken by inverters. φ φ

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 34 (November 27, 2000 6:34 pm)

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Single Phase Global Clock Generation Transistors in the inverter and pass gate should be similar in size. Keep them small and use buffers to drive the load. Note: The routing load MUST also be balanced on each of the clk lines. φ φ φ Buffers to drive large loads. Pass φ through a transmission gate as a means of calibrating for φ φ φ φ’s inverter delay.

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 35 (November 27, 2000 6:34 pm)

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Two-phase Global Clock Generation Clk φ1 φ2

1/0 1/0 1/0 1/0 0/1 0/1 0/1 0/1 1/0 1/0 0/1

Delay sets nonoverlap period. (time period in which both φ1 and φ2 are 0). Cross-coupled A B C D Clk φ2 φ1 A B C D RS fl ip-fl

• p

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 36 (November 27, 2000 6:34 pm)

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Multi-Phase Clocking Four-phase clocking strategies discussed in Weste and Eshraghian. Modern designs tend to minimize the number of clock phases used due to problem of generating and distributing multiple clocks. Single phase schemes used for complex, high-speed CMOS circuits.

Advanced VLSI Design CMOS Circuit Design CMSC 491C/691C 37 (November 27, 2000 6:34 pm)

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Clock Distribution Assume all the registers in a large CMOS design result in a capacitive load of 2000 pF. What is the peak current and average dynamic power? Two techniques: A single large buffer (cascaded inverters): Use when the module has a large number of diverse modules, i.e. a microprocessor. A distributed-clock-tree: Use when design is highly structured and repeti- tive, i.e. a datapath. VDD 5V = Cregister 2000pF 20K register bits @0.1pF ( ) = Tclock 10ns = T rise ( ) fall ( ) ⁄ 1ns = I peak Cdv dt

• 2000

12 – ×10 5 × 1.0 9 – ×10

• 10A

= = = Pd CVDD 2 f 2000 12 – ×10 25 100 6 ×10 × × 5watts = = =