DCDB4.x SiLab DEPFET crew University of Bonn paschen@physik.uni-bonn.de 1
What's new? from “ DCD Submission ” by Ivan from “ Status of Asics ” by Ivan in PXD bi-weekly SeeVogh Meeting in 20th International Workshop on DEPFET Detectors and Applications Tuesday, 10 November 2015 Thursday, 20 May 2016 Conservative version ● Both (4.x) ● As now with the following changes: larger LVDS bias current, ● JTAG sampling CLK edge changed to be compatible with in ADC layout added dummy structures, antenna diodes ● industry standard DCD digital driver strength can be optionally increased (from Main version 1 ● ● 1.3mA to 1.8mA) Changed sampling TCK edge ● Reference voltage can be increased by 30mV to cope with ● Programmable LVDS current (2 levels) ● waveform asymmetry. Programmable RefLVDS (2 levels, normal and by ~30mV ● Gain setting by 20% lower (feedback resistors 13k, 19k, 26k – ● increased) output resistor 15k) Gain settings redone ● IPDAC range reduced by factor 2 to improve granularity of offset ● IPDAC resized ● correction Parallel sampling mode for probe tests at full speed via JTAG, ● needle pads DCDB4.1 ● Defined power up sequence – VDDD should be turned on as ● Added two antenna diodes/cell and dummy structures to improve first ● the matching of transistors in ADC Separated bias DACs for up and down (for better LSB ● uniformity) DCDB4.2 In ADC layout added dummy structures, antenna diodes ● ● Changed layout to improve the matching ● Main version 2 New test-patterns for easier calculation of delay settings ● ● Changed ID code As version 1 with larger ADC transistors and uniform ● ● orientation for better matching and less missing codes Main version 3 ● As version 2 with new digital block – ID-code changed to one ● with LSB=1, added digital test patterns as proposed by Florian New type ● As version 3 with capacitive SAR ADC ● paschen@physik.uni-bonn.de 2
DCDB4.1 paschen@physik.uni-bonn.de 3
DCDB4.1 DCD-DHP communicatjon H5_0_13 “nominal” reference nominal LVDS current clock (76.2 MHz) paschen@physik.uni-bonn.de 4
DCDB4.1 DCD-DHP communicatjon H5_0_13 “nominal” reference increased LVDS current clock (76.2 MHz) paschen@physik.uni-bonn.de 5
DCDB4.1 ADC optjmizatjon H5_0_13 “nominal” reference ● Göttingen “low gain” optimum presented Wednesday 6/29 clock (76.2 MHz) ● IPSource/IPSource2: 80/75 ● Applied to H5_0_13 (DCDB4.1/Bonn): ● AmpLow/Refin: 350/800 ● IFBPBias: 80 ● Low Gain (en30, en60, en90) ● IampBias/Vtcsfn: 20/40 good channels 182 ● ITCP/ITCPL: 20/5 bit error channels 65 comp error channels 9 range error channels 0 ● High Gain (en30) good channels 112 bit error channels 134 comp error channels 10 unpleasant INL for range error channels 0 “Hybrid 5 matrix channels” paschen@physik.uni-bonn.de 6
DCDB4.1 ADC optjmizatjon H5_0_13 “nominal” reference ● Instead start more like previous DCDBv2pp: clock (76.2 MHz) ● IPSource/IPSource2: X/X ● AmpLow/Refin: 350/800-1000 ● IFBPBias: X ● IampBias/Vtcsfn: 60/60 ● ITCP/ITCPL: 30/30 + IFBref: 64 (new) → Amplow = 200 → Refin = 700 paschen@physik.uni-bonn.de 7
DCDB4.1 ADC optjmizatjon H5_0_13 “nominal” reference ● Instead start more like previous DCDBv2pp: clock (76.2 MHz) ● IPSource/IPSource2: X/X ● AmpLow/Refin: 350/800-1000 ● IFBPBias: X ● IampBias/Vtcsfn: 60/60 ● ITCP/ITCPL: 30/30 + IFBref: 64 (new) →IPsouce = 70 →IPsource2 = 60 paschen@physik.uni-bonn.de 8
DCDB4.1 ADC optjmizatjon H5_0_13 “nominal” reference ● Instead start more like previous DCDBv2pp: clock (76.2 MHz) ● IPSource/IPSource2: X/X ● AmpLow/Refin: 350/800-1000 ● IFBPBias: X ● IampBias/Vtcsfn: 60/60 ● ITCP/ITCPL: 30/30 + IFBref: 64 (new) → IFBPBias = 80 paschen@physik.uni-bonn.de 9
DCDB4.1 ADC optjmizatjon H5_0_13 “nominal” reference ● New optimum: clock (76.2 MHz) ● High Gain (en30) ● IPSource/IPSource2: 75/60 good channels 231 ● AmpLow/Refin: 200/700 bit error channels 11 ● IFBPBias: 80 comp error channels 14 ● IampBias/Vtcsfn: 60/60 range error channels 0 ● ITCP/ITCPL: 30/30 ● IFBref: 64 gain inhomogeneity, could it be solved median INL = 4.2 with adjusting Ipsource_middle? dcd-vdda = 1.8 V paschen@physik.uni-bonn.de 10
DCDB4.1 ADC optjmizatjon H5_0_13 “nominal” reference ● New optimum: clock (76.2 MHz) ● High Gain (en30) ● IPSource/IPSource2: 75/60 good channels 231 ● AmpLow/Refin: 200/700 bit error channels 11 ● IFBPBias: 80 comp error channels 14 ● IampBias/Vtcsfn: 60/60 range error channels 0 ● ITCP/ITCPL: 30/30 ● IFBref: 64 Still a bit of a kink, but tiny in comparison paschen@physik.uni-bonn.de 11
DCDB4.1 ADC optjmizatjon H5_0_13 “nominal” reference IFBPBias = 50 IFBPBias = 60 clock (76.2 MHz) channel 100 Ipsource/Ipsource2: 70/60 AmpLow/Refin: 200/700 IFBPBias = 70 IFBPBias = 80 → Higher IFBPbias can increase dynamic range and straighten ADC curve paschen@physik.uni-bonn.de 12
DCDB4.2 paschen@physik.uni-bonn.de 13
DCDB4.2 DCD-DHP communicatjon H5_0_26 “nominal” reference nominal LVDS current clock (76.2 MHz) paschen@physik.uni-bonn.de 14
DCDB4.2 DCD-DHP communicatjon H5_0_26 “nominal” reference increased LVDS current clock (76.2 MHz) paschen@physik.uni-bonn.de 15
DCDB4.2 ADC optjmizatjon H5_0_26 “nominal” reference ● Was not able to obtain good working point by scanning starting clock (76.2 MHz) from Ivan's settings either ● But also found probably good setting with different parameters: ● IPSource/IPSource2: 70/60 ● AmpLow/Refin: 200/650 ● IFBPBias: 70 ● IampBias/Vtcsfn: 60/60 ● ITCP/ITCPL: 30/30 ● IFBref: 64 paschen@physik.uni-bonn.de 16
DCDB4.2 ADC optjmizatjon H5_0_26 “nominal” reference ● IPSource/IPSource2: 70/60 clock (76.2 MHz) ● AmpLow/Refin: 200/650 ● IFBPBias: 70 ● IampBias/Vtcsfn: 60/60 ● ITCP/ITCPL: 30/30 ● IFBref: 64 paschen@physik.uni-bonn.de 17
DCDB4.2 ADC optjmizatjon H5_0_26 “nominal” reference ● IPSource/IPSource2: 70/60 clock (76.2 MHz) ● AmpLow/Refin: 200/650 ● IFBPBias: 70 ● IampBias/Vtcsfn: 60/60 ● ITCP/ITCPL: 30/30 ● IFBref: 64 paschen@physik.uni-bonn.de 18
DCDB4.2 ADC optjmizatjon H5_0_26 “nominal” reference ● IPSource/IPSource2: 70/60 clock (76.2 MHz) ● High Gain (en30) ● AmpLow/Refin: 200/650 good channels 240 ● IFBPBias: 70 bit error channels 9 ● IampBias/Vtcsfn: 60/60 comp error channels 7 ● ITCP/ITCPL: 30/30 range error channels 0 ● IFBref: 64 median INL = 3.9 dcd-vdda = 1.8 V paschen@physik.uni-bonn.de 19
DCDB4.2 ADC optjmizatjon H5_0_26 “nominal” reference ● IPSource/IPSource2: 70/60 clock (76.2 MHz) ● Low Gain (en30, en60, en90) ● AmpLow/Refin: 200/650 good channels 230 ● IFBPBias: 70 bit error channels 14 ● IampBias/Vtcsfn: 60/60 comp error channels 10 ● ITCP/ITCPL: 30/30 range error channels 2 ● IFBref: 64 median INL = 6.2 dcd-vdda = 1.8 V paschen@physik.uni-bonn.de 20
Conclusion ● First acceptable looking optimizations ● ITCP/ICTPL or IampBias/VTCSFN seemingly have to be choosen differently as compared to probe card setup ● AmpLow/Refin both lower than before ● IFBPBias is important ● Quality of “best settings” should be compared with previous DCD generation ● Further optimization may be possible ● All Scans done on two DCD4.2 and one DCD4.1 Hybrid 5 in Bonn can be viewed and downloaded here (spreadsheet and .zip files): https://drive.google.com/open?id=0B9HoVIkUMp-RcTljbkZUSWJpTUU paschen@physik.uni-bonn.de 21
Thank you paschen@physik.uni-bonn.de 22
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