SLIDE 1
1
DCDB4.x
SiLab DEPFET crew University of Bonn
paschen@physik.uni-bonn.de
What's new?
paschen@physik.uni-bonn.de 2
from “DCD Submission” by Ivan
in PXD bi-weekly SeeVogh Meeting Tuesday, 10 November 2015
- Conservative version
- As now with the following changes: larger LVDS bias current,
in ADC layout added dummy structures, antenna diodes
- Main version 1
- Changed sampling TCK edge
- Programmable LVDS current (2 levels)
- Programmable RefLVDS (2 levels, normal and by ~30mV
increased)
- Gain settings redone
- IPDAC resized
- Parallel sampling mode for probe tests at full speed via JTAG,
needle pads
- Defined power up sequence – VDDD should be turned on as
first
- Separated bias DACs for up and down (for better LSB
uniformity)
- In ADC layout added dummy structures, antenna diodes
- Main version 2
- As version 1 with larger ADC transistors and uniform
- rientation for better matching and less missing codes
- Main version 3
- As version 2 with new digital block – ID-code changed to one
with LSB=1, added digital test patterns as proposed by Florian
- New type
- As version 3 with capacitive SAR ADC
from “Status of Asics” by Ivan
in 20th International Workshop on DEPFET Detectors and Applications Thursday, 20 May 2016
- Both (4.x)
- JTAG sampling CLK edge changed to be compatible with
industry standard
- DCD digital driver strength can be optionally increased (from
1.3mA to 1.8mA)
- Reference voltage can be increased by 30mV to cope with
waveform asymmetry.
- Gain setting by 20% lower (feedback resistors 13k, 19k, 26k –
- utput resistor 15k)
- IPDAC range reduced by factor 2 to improve granularity of offset
correction
- DCDB4.1
- Added two antenna diodes/cell and dummy structures to improve
the matching of transistors in ADC
- DCDB4.2
- Changed layout to improve the matching
- New test-patterns for easier calculation of delay settings
- Changed ID code