filtering for trigger primitive Ba Babak Abi UK DUNE firmware - - PowerPoint PPT Presentation

DPM firmware R&D filtering for trigger primitive

Ba Babak Abi

UK DUNE firmware Meeting

30 30 May 20 2018 18

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DPM Fir irmware R&D

• Three main aims :

I. DUNE’s new DPM initial tests. (Oct 2018)

• RAM & SSD checking, High speed lines (10Gbps). This firmware would be used also in production/commissioning
• Hardware platform; New COB !, Jig Board?

II. Estimating the FPGA resource needed v.s. various TPC performance level (high to low noise).

• Full or partial implementation of blocks of next slide
• Some data process and functions are not shown and the buffer block has several sub-blocks

III. ProtoDUNE data, real performance check for trigger primitives.

• Need to changed to WIB interface , some firmware exist, reuse them?
• Some blocks like timing and trigger candidate can be emulated, some like SSD buffer can be removed.
• Using SLAC’s FPGA Build Systems & Libraries, RCE Core Firmware.
• Centralized build and code with lots of libs
• Still there are blocks and places need effort
• The Trigger primitives related blocks need more realistic detector simulation

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DPM Fir irmware R&D

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Sub Projects How much exist already Where 1-CORE PS/PL Ryan/Larry 2-Compression PL J.J. 3-TPC Interface PL ? 4-Data Splitter PL ? 5-Filter PL Roy, Babak, Peter 6-Hit Finder PL J.J. 7-10GE(TCP) In core PL/PS ? 8- Buffer controller - DDR4 PL/PS ? 9- Buffer controller - SSD PS Roy, Babak, Peter 10-GE(serial FELIX) PL ? 11- PS C++ PS ? 12-Time/Trigger Block PL Bristol + ?

Fil iltering scheme <-> Noise

• For R&D and study filter TPG performance we had suggested a data challenge

approach (talks on https://indico.fnal.gov/event/15347/contribution/6 and https://indico.fnal.gov/event/15612/contribution/2):

1) Start with a MC with all physics signal (SN, …) and physics background (radiological,..) and a minimum white noise. 2) Create the python/C++ script with parametrised realistic (as much we understand TPC performance) noise + signal distortion models. 3) Add the noise to extracted raw signal from MC and Run your TPG (hit finder+filter+…) algorithm and extract the performance, efficiency, fake rate, TPG data rate,… 4) Change the parameter or model and study performance and estimate Max/Min resource you need for your TPG based on noise level and model.

1. Current noise implementation: 1)LV regulator FEM level dependency 2)HV plate 3) Pedestal drift 4)non-steady Noise amplitude (Miquel will show in the talk soon)

• 2. Filter specifications:
• How many taps, Classification, X-Pass filter.
• Different Filter per channels? Configurable filter?

3. Filter implementation; either VHDL or HLS and Pipelining optimization

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Back up slides

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Noise and sig ignal dis istortion: sources

• Noise sources, Model, Characteristics; three types of noise in TPC:

1. Fundamental noise (white/pink noise,…)

• Comes from analog readout, proportional to the total capacitive load on the input

channel(wire length,..) and channel independent

• Simulated already in a basic level in MC

2. Parasitic and EMI (pickup noise, HV/LV PSs ….)

• Location (channels& ) dependency
• Coherent noise spectrum characteristics is steady through time! Might need to be

monitored daily bases (done offline )

• Not simulated in MC

3. Detector noise (Microphonic, ..)

• characteristics is not steady!?
• Signal distortion
• 1. Pedestal drift, variable Noise ,broken channels

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• Trigger primitive generation only on Collection?
• Induction plane are better even after filtering because they are bipolar
• Should we use all channels ?

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Collection Plane Induction Plane

• Noise has been

added

DATA with Higher Noise