Systems Delays Shankar Balachandran* Associate Professor, CSE - - PowerPoint PPT Presentation

Shankar Balachandran* Associate Professor, CSE Department Indian Institute of Technology Madras

*Currently a Visiting Professor at IIT Bombay

Digital Circuits and Systems

Spring 2015 Week 5 Module 24

Delays

RC Delay Model

 Use equivalent circuit for transistors  Ideal switch + capacitance and ON resistance

 Unit nMOS has resistance R, capacitance C  Unit pMOS has resistance 2R, capacitance C

 Capacitance proportional to width  Resistance inversely proportional to width

Delays 2

Inverter

Delays 3

Delay = 6RC

Delays 4

Timing Parameters

 Rise Time (tr), the time required for a signal to transition

from 10% of its maximum value to 90% of its maximum value.

 Fall Time (tf), the time required for a signal to transition

from 90% of its maximum value to 10% of its maximum value.

 Propagation Delay (tpLH, tpHL), the delay measured from

the time the input is at 50% of its full swing value to the time the output reaches its 50% value.

Delays 5

Timing parameters (contd…)

time Vin Vout time Vmax 0.5Vmax 0.5Vmax Vmax 0.9Vmax 0.1Vmax tpLH tpHL tr tf

• Gate delays and the corresponding waveform representation capture the dynamic

behavior of a circuit. The propagation path that determines the delay through the circuit is called the critical path.

Delays 6

Timing Analysis of Combinational Circuits

 Using gates with finite propagation delays, tpLH and tpHL

instead of zero gate delays used in functional analysis.

Gate tpLH tpHL INV 3 ns 2 ns XOR 5 ns 4 ns

Delays 7

Vin V1 V2 V3 Vout

t=0 4 2 3 2 5 8 ns

0→1 Transition on Vin Vin V1 V2 V3 Vout

4 3 2 3 5 9 ns

1→0 Transition on Vin

Gate tpLH tpHL INV 3 ns 2 ns XOR 5 ns 4 ns

Delays 8

Example: Gate delay

 Determine the worst case propagation delay through these

circuits.

     

 

max 2 5 , 3 5 , 3 8

p

t gd    

2 ns 4 ns 2 gd 3 gd 5 gd

2 4 6

p

t ns   

2 gd 3 gd 5 gd 3 gd 6 gd

       

 

max 2 5 , 3 5 , 3 , 6 3 9

p

t gd     

Delays 9

Gate Delay Reality!

 The time delay of a gate is affected by the following:

 Intrinsic delay of the gate, i.e., delay due to internal load.  Fanout (load) dependent delay. Delay of a gate increases as its

fanout (capacitive load in CMOS) increases.

 Fanin dependent delay. Gates with high fanin have high delay.  Supply voltage fluctuations affect delay. Delay decreases with

increase in supply voltage (to some extent only!).

 Simple gate delay model for CMOS gates:

p int load load

t t t C  

intrinsic delay (ns) load dependent delay (ns/fF) total load (fF) = capacitive load due fanout gates + interconnecting wires

Delays 10

Gate Delay Example:

Gate Input

• Cap. (fF)

Delay tp (ns) CL in fF NOT 10 0.05 + 0.017CL AND2 15 0.15 + 0.037CL AND3 20 0.20 + 0.038CL OR2 15 0.20 + 0.019CL OR3 20 0.34 + 0.022CL

             

1 2 3 4 5 6 7

0.05 0.017 2 15 2 20 1.24 0.15 0.037 15 0.705 0.34 0.022 20 0.78 0.34 0.022 20 0.78 0.20 0.019 20 0.58 0.20 0.019 4 10 0.96 0.20 0.038 4 10 1.72 t ns t ns t ns t ns t ns t ns t ns                          

Assume a fanout of 4 NOTs load at each output.

 

 

 

2 6 4 7 2 6 3 7 1 6 4 1 3 5 7 4 5 7

critical 1.665 2.5 1.665 2.5 2.115 max , max , 3.74 max , 2. paths: 7 5

• 3. 4

a x a p z b x b z c x c z d z

t t t ns t t t ns t t t ns t t t ns t t t ns t t t t t t ns t t t t n c z t ns s

      

                         

c a b d x z

1 2 3 4 5 6 7

End of Week 5: Module 24

Thank You

Delays 11