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Trigger for Phase 1 Marco Bellato, Fabio Montecassiano, Andrea - PowerPoint PPT Presentation

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Trigger for Phase 1 Marco Bellato, Fabio Montecassiano, Andrea Triossi, Sandro Ventura CMS Week, CERN, 11 Nov 2012 1 DT Layout after Relocation UXC USC Cu OF Sector Server Board DTTF OF Cu Collector TwinMux DTTF No schedule

  1. Trigger for Phase 1 Marco Bellato, Fabio Montecassiano, Andrea Triossi, Sandro Ventura CMS Week, CERN, 11 Nov 2012 1

  2. DT Layout after Relocation UXC USC Cu OF Sector Server Board DTTF OF Cu Collector TwinMux µDTTF • No schedule interference for achieving Schedule: validation tests 2015 – validation on a slice • Backward compatible with old SC links 2016 – full deployment 2

  3. TwinMux I/O Requirement TwinMux input link count • 2 sectors served per card • 64x480Mbps LVDS pairs from minicrate • 12x1.6Gbps GOL links from old SC TwinMux output link count • 2 sectors served per card (64x480Mbps ≈ 30Gbps) • 2x10Gbps links needed per sector to ship all data • 3 copies of links for redundancy 6 links per sector 12 links total 3

  4. TwinMux 30 µTCA 1-slot board Level De-mux Translator GTX GTX SNAP12 TX SNAP12 RX KINTEX-7 CML Sele to ctIO LVDS JDSU Xilinx Micrel Micrel Avago PL-RCP-02-S53-11 XC7K355T SY58024U SY55855V AFBR-810 64 @ 480Mbps from CUOF Input: Max Output: 12 @ 10Gbps to DTTF or 12 @ 1.6Gbps from SC 6 front panel SNAP12 RX and 1 TX on the back (no rear transition module) 4

  5. D. Acosta 5

  6. D. Acosta 6

  7. Full DT Trigger Chain 192 Gbps Tracker 4800 bit/BX RPC (phase II) 2x6.4 Gbps µDTTF GMT ..... Twin 64 µDTTF Mux 480 Mbps µDTTF 640 bit/BX 80 bit/BX SP CSCTF . . . . . . . . . . 820 Gbps 80 Transceivers MP7 µDTTF ..... Twin 64 µDTTF Mux µDTTF 740 Gbps 72 Transceivers 30 boards 12 boards 7

  8. Data Structure Bit Signal Name Signal Function 0 - 11 PHI_ST1a_0 - PHI_ST1a_11 12 bit Phi (Position) of Station #n UP 12 - 21 PHIB_ST1a_0 - PHIB_ST1a_9 10 bit Phi_b (Bending Angle) of Station #n UP 22 - 24 Q_ST1a_0 - Q_ST1a_2 3 bit Quality of Station #n UP 25 TSTAG_ST1a 1 bit Second TS Tag of Station #n UP 26 CCB_RDY_ST1a ccb_ready Station #n UP 27 CALSIG_ST1a 1 bit Control (Calibration Data) of Station #n UP 28 BC0_ST1a Bunch Crossing Zero Bit Station #n UP 29 PAR_ST1a Parity over data from Station #n UP 30 - 37 ETA_HIT_ST1_0 - ETA_HIT_ST1_7 8 Eta hit bits of Station #n 38 - 39 BXCNT_ST1a_0, BXCNT_ST1a_1 2 bit BX Counter LSbits of Station #n 40 - 51 PHI_ST1b_0 - PHI_ST1b_11 12 bit Phi (Position) of Station #n DOWN 52 - 61 PHIB_ST1b_0 - PHIB_ST1b_9 10 bit Phi_b (Bending Angle) of Station #n DOWN 62 - 64 Q_ST1b_0 - Q_ST1b_2 3 bit Quality of Station #n DOWN 65 TSTAG_ST1b 1 bit Second TS Tag of Station #n DOWN 66 CCB_RDY_ST1b ccb_ready Station #n DOWN 67 CALSIG_ST1b 1 bit Control (Calibration Data) of Station #n DOWN 68 BC0_ST1b Bunch Crossing Zero Bit Station #n DOWN 69 PAR_ST1b Parity over data from Station #n DOWN 70 - 77 ETA_Q_ST1_0 - ETA_Q_ST1_7 8 Eta quality bits of Eta Station #n 78 BC0_ST1b BC0 signal bit of Eta Station #n 79 TRG_ST1 Trigger bit of Station #n Bit Station #n 0 - 79 1 80 - 159 2 160 - 239 3 240- 319 4 8

  9. Common Developments RPC link count • 29x1.6Gbps GOL links per wedge 348 input links in total • 6 to 1 links mux 5x9.6Gbps links per wedge • 3 copies of links for redundancy 15 links per wedge 180 links total ROS? • 10Gbps lane on backplane to AMC13? • Virtex? 9

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