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Towards Probabilistic Timing Analysis for SDFGs on Tile Based - - PowerPoint PPT Presentation

Nov 06, 2022 122 likes •381 views

EMBEDDED REAL TIME SYSTEMS 2020 Towards Probabilistic Timing Analysis for SDFGs on Tile Based Heterogeneous MPSoCs Ralf Stemmer 1 Hai-Dang Vu 2 Kim Grttner 3 Sbastien Le Nours 2 1 University of Oldenburg, Germany Wolfgang Nebel 1 2 University

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EMBEDDED REAL TIME SYSTEMS 2020

Towards Probabilistic Timing Analysis for SDFGs

  • n Tile Based Heterogeneous MPSoCs

1 University of Oldenburg, Germany 2 University of Nantes, France 3 OFFIS e.V., Germany

ERTS‘20, France, 29th January 2020

DAAD with funds from the Federal Ministry of Education and Research (BMBF) CampusFrance with funds from the French Ministry of Europe and Foreign Afgairs (MEAE) and by the French Ministry for Higher Education, Research and Innovation (MESRI)

Ralf Stemmer 1

Hai-Dang Vu 2 Kim Grüttner 3 Sébastien Le Nours 2 Wolfgang Nebel 1 Sébastien Pillement 2

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Motivation

Software t t t

€€€ €€ ? €

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Approach

Models of Computation and Architecture Configuration Simulation Delay Annotation

Sofuware Product Hardware Characterization Analysis / DSE Deployment Modeling Hardware Sofuware Time Simulation

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Computation Model

Execution Phases

A0 A1 1 1 1 1

Token Rate Channel Actor Compute Write Read

A2 t

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Computation Model: Constraints

Self Scheduled No Interruption Blocking FIFO Bufger Isolated Compute Phase Execution Phases

A0 A1 1 1 1 1

Token Rate Channel Actor Compute Write Read

A2 t

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Platform Model

Execution Phases

A0 A1 1 1 1 1

Token Rate Channel Actor Compute Write Read

A2 t

Tile n Tile 0 Processing Element Memory Processing Element Shared Memory Interconnect

...

Memory

FPU

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Platform Model: Constraints

Tile 0 1 Token = 1 Data Word on Bus

A2

1 Shared System Bus Tile n No Caches Static RAM Processing Element Memory Processing Element Shared Memory Interconnect

...

Local Memory Memory Execution Phases

A0 1 1 1 1

Token Rate Channel Actor Compute Write Read

t A1

FPU

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Designflow: Modeling

Sofuware Actors Tiles-Types Shared Resources Hardware Hardware Sofuware Time Simulation

Delay Annotation

Characterization

Configuration Simulation

Product Analysis / DSE Deployment Modeling

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Characterization

Tile Type B Tile Type A Memory Memory Actors × Tile Type Shared Memory Interconnect

A0 A1 1 1 1 1

Token Rate Channel Actor

A2

Processing Element A0 A1 A2 Processing Element A0 A1 A2

FPU

Channels

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Characterization: Computation

Shared Memory Channels Tile Type B Tile Type A Memory Memory Actors × Tile Type Measurement Infrastructure Interconnect

A0 A1 1 1 1 1

Token Rate Channel Actor

A2

Actors Tiles

Processing Element A0 A1 A2 Processing Element A1 A2

FPU

HIP3ES'17 – C. Schlaak, M. Fakih and R. Stemmer – "Power and Execution Time Measurement Methodology for SDF Applications on FPGA-based MPSoCs"

A0

start(); A0(&out1, &out2); stop();

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Characterization: Communication

Tile Type B Tile Type A Memory Memory Shared Memory Measurement Infrastructure Interconnect Channels

Actors Tiles

Processing Element A0 A1 A2 Processing Element A0 A1 A2

FPU

Actors × Tile Type

A0 A1 1 1 1 1

Token Rate Channel Actor

A2

SAMOS'19 – R. Stemmer, H.-D. Vu, K. Grüttner, S. Le Nours, W. Nebel and S. Pillement – "Experimental Evaluation of Probabilistic Execution-Time Modeling and Analysis Methods for SDF Applications on MPSoCs"

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Characterization: Constraints

Tile Type B Tile Type A Memory Memory Actors × Tile Type Shared Memory Interconnect Channels

A0 A1 1 1 1 1

Token Rate Channel Actor

A2

Actors Tiles

Dedicated Interconnect On-Chip / Ofg-Chip Measurement Infrastructure Processing Element A0 A1 A2

FPU

Processing Element A0 A1 A2

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On-Chip Measurement

MPSoC Measurement Infrastructure On-Chip Measurement

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Ofg-Chip Measurement

MPSoC Measurement Infrastructure Ofg-Chip Measurement

Photo: Ralf Stemmer, 2019

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Designflow: Characterization

Sofuware Actors Tiles-Types Computation Model Shared Resources Measurements Communication Model Hardware Characterization Hardware Sofuware Time Simulation Measurement Infrastructure Modeling

Configuration Simulation

Product Analysis / DSE Deployment FPGA /

  • Eval. Board

⚙

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Simulation

Computation Models Communication Model Difgerent Mappings

A2

Computation Models Token Storage

...

A0 A1

A0 A1 1 1 1 1 A2

Tiles Actors T0 T1 T2 Mem. FPU Interconnect

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Simulation: Details

Computation Models Communication Model Difgerent Mappings

A2

Computation Models Token Storage

...

A0 A1

A0 A1 1 1 1 1 A2

Tiles Actors T0 T1 T2 Mem. FPU Interconnect Mappings

ReadTokens(ChA); wait(GetDelay(DistA2)); ReadTokens(ChA, in); A2(in);

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Designflow

Sofuware Actors Tiles-Types Computation Model Shared Resources Simulation Mapping / Configuration Evaluation Product Measurements Communication Model Hardware Characterization Analysis / DSE Deployment Hardware Sofuware Time Simulation Measurement Infrastructure Modeling FPGA /

  • Eval. Board

⚙

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Example: JPEG Decoder

Get MCU IQY IQCr IQCb IDCTY IDCTCr IDCTCb YCrCb RGB 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 3 3 3 MUL FPU

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JPEG Decoder: Characterized

Get MCU IQY IQCr IQCb IDCTY IDCTCr IDCTCb YCrCb RGB 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 3 3 3 MUL FPU Tiles Actors IQY IQCr IQCb IDCTY IDCTCr IDCTCb YCrCb RGB Get MCU MUL FPU

OOM OOM

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Example Hardware

T0 Shared Memory Interconnect T0 T1 T2 Shared Memory

MUL FPU

Interconnect T0 T1 T2 T3 T4 T5 T6 Shared Memory

FPU FPU FPU MUL MUL MUL

Interconnect

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Simulative Comparison

T0 Shared Memory Interconnect T0 T1 T2 Shared Memory

MUL FPU

Interconnect T0 T1 T2 T3 T4 T5 T6 Shared Memory

FPU FPU FPU MUL MUL MUL

Interconnect Avg: 0.94 · 106 WCET: 1.19 · 106 Avg: 0.93 · 106 WCET: 1.18 · 106 Avg: 2.39 · 106 WCET: 2.77 · 106

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Evaluation

JPEG, 1 Tile JPEG, 3 Tile JPEG, 7 Tile < 1 min 0:39 1:47 13:15 5:13 5:13

ERTS‘20

0.17 % 0.05 %

  • 1.52 %

2.52 % 7.73 % 7.31 % Experiment Simulation Measurement Simulation Static Math. Duration [HH:MM] WCET Error JPEG, 3 Tiles

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Conclusion

t t t

– Tiles – Caches – Data Dependency

+ Characterization + Distribution + Accuracy vs. Speed + Easy Integration