Tota otal S Sens ensitivity B Bas ased ed DFM FM Optimiz - - PowerPoint PPT Presentation

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Tota

• tal S

Sens ensitivity B Bas ased ed DFM FM Optimiz mizat ation ion of

• f

Standar ndard L d Library Cells lls

Yongchan Ban, Savithri Sundareswaran*, and David Z. Pan ECE Dept., The University of Texas, Austin, TX *Freescale Semiconductor, Austin, TX

TM

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Outline line

 Motivation  Our Contribution  Total Sensitivity

› Device criticality based sensitivity › Lithography proximity induced sensitivity › Process variation induced sensitivity

 Total Sensitivity Based Layout Optimization  Experimental Results  Conclusions

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Current Lithography Challenges

1980 1990 2000 2010 2020 10 1 0.1 um

 Optical lithography (193nm) will continue for several years.

› Immersion, RET (Resolution Enhancement Technique, e.g. OPC) › DPL (Double Patterning Lithography)

 Next Generation Lithography (e.g. EUV)

› Economical/material/technical challenges

[Courtesy Intel]

[Courtesy Intel, 2006]

• nce

Gate Variation @ Standard Cell

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Line-end Shortening Active Corner Rounding Poly Corner Rounding Process Variation

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Impact of Gate Length Variation

 ΔLgate is up to 10% @45nm node.  The small improvement of ΔLgate reduction can leads to

significant decrease of delay and leakage variations.

• 10 -8 -6 -4 -2

2 4 6 8 10

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• 20
• 10

10 20 30 NMOS PMOS

Delay Variation (%) Length Variation (%)

• 10 -8 -6 -4
• 2

2 4 6 8 10 10

• 1

10 10

1

10

2

NMOS Leakage

Leakage Variation (%) Length Variation (%)

Over 20% 40X

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Standard Cell Layout Optimization

 Since a lot of identical cells will be used repeatedly, any

small changes can result in significant improvements.

 Restricted design-rules in industry [Choi’07 SPIE,Liebmann’09 SPIE]

› Rule based and simple › Large number of rules and expensive rule checking › RDR is starting to fail in their attempt to use a discrete modeling approach on a continuous systems.

 Lithography model based optimization [Cote’04 ISQED,Tang’08 SPIE]

› Robust layout for nominal lithography › No consider device criticality in circuit level › No single metric for both lithography proximity and process variation

 New model-based approach is needed.

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Our Contributions

 Timing Criticality

› The variation for a high sensitive device should be as small as possible.

 Process Criticality

› Minimize the difference between fastest and slowest process corner

 Total Delay Sensitivity Modeling

› Circuit Topological Delay Sensitivity › Lithography Proximity Induced Sensitivity › Process Variation Induced Sensitivity

 Delay, Leakage and Process Robust Layout

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Device Criticality Based Sensitivity

 Delay variation for the delay arc, α due to variation, ΔLi :  Total delay sensitivity index, Ψ:  The devices within the cell can be ranked.  Circuit induced

sensitivity  σ

∑

∆ ∂ ∂ = ∆

α α i i i

L L d d

∑ ∑

∆ ⋅ = ∆ ⋅ = Ψ

i i

L d σ ω

α α α

PMOS NMOS

σ = σ

PMOS NMOS

σ < σ

PMOS NMOS PMOS NMOS

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) , ( ω

x y y

L f e L ∆ ∝ ∂ ∂

Lithography Proximity Sensitivity

 Transversal (ΔLx) variation and

Longitudinal (ΔLy) variation

 ΔLx: EPE as a function of Δex.  ΔLy is changed from different conduction  Lithography proximity

Induced sensitivity  γ

i x i x i x i x

e e L L

, , , ,

∆ ∂ ∂ = ∆

i y y y y

L e e L L ∆ = ∆ ∂ ∂ = ∆

poly printimage Δex epe

Transversal

poly printimage Δey

Longitudinal

ω is a weighting factor of narrow width effect

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Process Variation Induced Sensitivity

 Dose and focus errors are the dominant sources  Given focus level, Δpf , ΔL can be simplified:  Process induced sensitivity

 η

2 f 2 f 2 e e

p p L p % p ln L L ∆ ∂ ∂ + ∆ ∂ ∂ = ∆

±Δpe Δpf

symme metric

e 2 f F e

p % ] p 1 [ p ln L L ∆ ⋅ ∆ ⋅ α + ∂ ∂ = ∆

e p e

p p L

f

∆ ⋅ ∂ ∂ =

∆

% ln

Three Metrics of Sensitivity

 Device Criticality  σ  Lithography Proximity Sensitivity  γ  Process induced sensitivity  η

∑

∆ ⋅ = Ψ

i i

L σ

y y y i

e e L L ∆ ∂ ∂ = ∆

e p e i

p p L L

f

∆ ± ⋅ ∂ ∂ = ∆

∆

% ln σ

Slowest~+η Nominal~γ Fastest~-η

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Correlation Betw een γ and η

 The process sensitivity (η) is highly correlated with the

lithography proximity sensitivity (γ).

 Once γ is calculated, we can estimate η.  We should minimize the process gap (Slowest - Fastest).

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• 20
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10 20

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• 20
• 10

10 20

positive ∆p negative ∆p linear fit linear fit

Process Sensitivity (η∆p [%CD]) Proximity Sensitivity (γ∆e [%CD])

nominal

γ + γ − η

smaller

η

larger

Fastest process corner Slowest process corner

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Total Sensitivity

 Device criticality aware layout  Process-robust layout

∑

        ∆ ± ⋅ ∂ ∂ + ∆ ∂ ∂ ⋅ σ = ∆ ⋅ σ = Ψ

∆ j e p e i y y j , i i i i i

p % p ln L e e L L

f

( )

e y

p % , e i i i ∆ ± ∆

η + γ ⋅ σ =

     y sensitivit process y sensitivit proximity y criticalit device

i i i

_ : _ : _ : η γ σ

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Poly / Active Layer Optimization

 Poly corner to active (PCA)  positive ΔLgate  Poly line-end (PLE)  negative ΔLgate  Active corner to poly (ACP)  positive ΔWgate

Poly Layout Optimization Active Layout Optimization

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10 20 30 40 50 60 70 3 6 9 12 15 18

Normalized ∆Leff Convex fit Normalized ∆d Convec fit

Distance (Poly PAD to Active) [nm] Normailized ∆Leff [nm]

• 10

10 20 30 40 50 60

Normalized ∆d [%]

6 9 12 15 18

• 1.8
• 1.5
• 1.2
• 0.9

Normalized ∆Leff Linear fit Normalized ∆d Linear fit

Distance (Line-end to Active) [nm] Normailized ∆Leff [nm]

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• 7
• 6
• 5
• 4

Normalized ∆d [%]

Poly Layer Optimization

 PCA shows a convex form (-1/√x) in our DRC range.  PLE has a positive linear trend in a certain range.

PCA PLE

c PLE b PCA a

i i ij

+ ⋅ + ⋅ ≥ γ e p d

ij i ij

+ ⋅ ∆ ⋅ ≥ γ η

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Poly Layer Optimization

 The objective is to minimize the maximal delay variation.  Since γij is convex, we can obtain optimal PCA and PLE.

min , max , ij ij

d d ∆ + ∆ min:

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• 20
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10 20

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• 20
• 10

10 20

positive ∆p negative ∆p linear fit linear fit

Process Sensitivity (η∆p [%CD]) Proximity Sensitivity (γ∆e [%CD])

p e i S j ij ij i ij

y

d

∆ ∆ ∈

∑

+ ≥ ∆

,% ) ( max ,

) ( η γ σ

p e i S j ij ij i ij

y

d

∆ ∆ ∈

∑

− ≤ ∆

,% ) ( min ,

) ( η γ σ c PLE b PCA a

i i ij

+ ⋅ + ⋅ ≥ γ e p d

ij i ij

+ ⋅ ∆ ⋅ ≥ γ η

s.t.:

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20 30 40 50

• 3.0
• 2.5
• 2.0
• 1.5
• 1.0
• 0.5

0.0 Normalized ∆Leff Linear fit Normalized ∆d Linear fit

Distance (Avtive Rail to Poly) [nm] Normalized ∆Leff [nm]

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• 8
• 6
• 4
• 2

2

Normalized ∆d [%]

Active Layer Optimization

 ACP has a positive linear trend with the distance

• f active corner to poly.

 The objective is to

minimize gate proximity.

 γij is linear, we can obtain

• ptimal ACP.

b ACP a

i ij

+ ⋅ ≥ γ

y

e i S j ij i ij

d

∆ ∈

∑

≥ ∆

) ( max ,

γ σ min: s.t.:

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Layout Statistical Characterization Device Criticality σi, OPC/Lithography Total Sensitivity Active Optimization Schematic

( )

p e i i i

y

∆ ∆

+ ⋅

,%

η γ σ

Poly Optimization Layout Extraction Cell Characterization Convex Formula Linear Formula

Overall Flow

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Exper eriment ment R Result ults: S : Setup up

 Impletemeted in Tcl/Perl  Industrial 45nm ASIC designs  Calibre-WB for model based OPC/Litho  H-Spice for timing/characterization  Two Layout Optimizations

› Conventional restricted design rule (RDR) approach (CONV) › Total sensitivity based layout optimization (TSDFM)

Delay Variation

 Δdelay @best process is relatively low (around 3%)  Up to 24% reduction in the delay difference between the

fastest and the slowest process corner.

5 10 15 20 25 CKT-BEST PV CKT-PV RDR TSDFM

The Delay Variation [%] 43% 8% 16%

* Average delay for entire cells

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Leakage Variation

 The local maximum leakage is decreased up to 91.9% in

a cell and as much as 57.5% on average.

 Despite the small improvement of ΔL, we can see the

huge amount of improvement on leakage current.

Cell ΔL Leakage ΔL Leakage Improve CONV TSDFM %

C1

• 2.26

2.289E-08

• 1.27

5.407E-09 85.12 C2

• 1.28

5.434E-09

• 0.94

4.619E-09 26.45 C3

• 1.83

6.747E-09

• 1.19

5.203E-09 35.13 C4

• 2.90

3.082E-08

• 1.08

4.940E-09 90.91 C5

• 1.43

5.789E-09

• 1.33

5.546E-09 7.07 C6

• 1.86

6.808E-09

• 0.54

3.639E-09 71.12 C7

• 2.03

2.002E-08

• 1.78

6.630E-09 75.78 C8

• 2.76

2.917E-08

• 1.18

5.178E-09 89.46 C9

• 2.29

2.332E-08

• 1.54

6.046E-09 82.38 C10

• 2.79

2.945E-08

• 2.54

2.637E-08 11.37

Conclusions

 Total sensitivity (device criticality, nominal

lithography proximity, process variation)

 The process sensitivity is highly correlated with

the lithography induced sensitivity.

 Optimization is done by reducing the gap

between the fastest and slowest delay corner. (up to 25% reduction of Δdelay and 92% decrease of leakage)

 Future works

› Metal proximity & interconnect optimization › S/D contact optimization

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Acknow ledgments

 This work is supported in part by SRC,

NSF CAREER Award, and equipment donations from Intel.

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Back-up slide

 Delay variation for the delay arc, α due to variation, ΔLi :  Total delay sensitivity index, Ψ:  The devices within the cell can be ranked.  Circuit induced sensitivity  σ

∑

∆ ∂ ∂ = ∆

α α i i i

L L d d

∑ ∑∑ ∑

∆ ⋅ σ = ∆ ∂ ∂ ⋅ ω = ∆ ⋅ ω = Ψ

α α α α α α i i i i i

L L L d d

i i i

L L d d ∆ ∂ ∂ = ∆

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