INVENTIVE CONFIDENTIAL DfM: What, Why, When & How Nickhil - PowerPoint PPT Presentation

INVENTIVE CONFIDENTIAL DfM: What, Why, When & How Nickhil Jakatdar

Overview: • What is DfM? • Why DfM? – The realities below 130nm – Yield / Cost Analysis – Rules and Models • When is it going to be needed? – Examples in CMP, Lithography, and CAA • How is it going to be solved? – Novel approaches in design implementation • Observations and Predictions February 16, 2007 Cadence Confidential: Cadence Internal Use Only 2

What is Design for Manufacturing (DfM)? • Various definitions of DfM include – Anything and everything relating to a more mfg. aware design of a chip – RET/OPC – Lithography/CMP Process Checks – Critical Area Analysis – Statistical Static Timing Analysis (SSTA) – Manufacturing Aware Routers – Design for Marketing – Design for Money – Anything that allows a start-up to raise a round of funding February 16, 2007 Cadence Confidential: Cadence Internal Use Only 3

Overview: • What is DfM? • Why DfM? – The realities below 130nm – Yield / Cost Analysis – Rules and Models • When is it going to be needed? – Examples in CMP, Lithography, and CAA • How is it going to be solved? – Novel approaches in design implementation • Observations and Predictions February 16, 2007 Cadence Confidential: Cadence Internal Use Only 4

Why Design must care about Manufacturing… • Below 130nm, “What you draw is not what you get” • The further you go below 130 nm, the less a rule-based approach is effective • This leads to designs that behave very differently in reality vs. simulation � little to no predictability Illustration and photomicrograph courtesy of Texas Instruments. February 16, 2007 Cadence Confidential: Cadence Internal Use Only 5

More and more Manufacturing Effects cannot be Modeled with Rules 130nm 65nm/45nm Via Via Failure Failure Particle Particle Defects Defects Litho Effects CMP Effects Timing, Power Variation February 16, 2007 Cadence Confidential: Cadence Internal Use Only 6

Impact of DfM on Yield Increasing with each new process generation Yield σ : ±5% Yield σ : +5% to -50% 100 Random Process-Related 90 Systematic Reticle-Related 80 (RET impact) Systematic 70 Nominal Yields (%) Design-Related 60 (leakage, performance, 50 power) 40 30 20 10 0 0.35µm 0.25µm 0.18µm 0.13µm 90nm Source: IBS Feature Dimension February 16, 2007 Cadence Confidential: Cadence Internal Use Only 7

Impact of DfM on Design Costs Observations: 100.0 � Design-specific yield related problems are growing 80.0 Design Design Costs ($M) Costs 60.0 � Caused by interaction of design & materials/process 40.0 DFM /DFY � Increasing cross-process Costs 20.0 interactions difficult to model with rules 0.0 0.18µm 0.13µm 90nm 65nm � Most solutions lie beyond the T echnology N ode domain of Traditional DFM (e.g. post design processing) February 16, 2007 Cadence Confidential: Cadence Internal Use Only 8

Impact of DfM on Time to Market Effectivity of Iteration Cost of Iteration RTL $ Implementation $$ Signoff MFG $$$ Expected Volume Shipment Schedule Delay $$$$ $$$$$$$ $$$$$$$$$$$$$ Actual Volume Shipment February 16, 2007 Cadence Confidential: Cadence Internal Use Only 9

Traditional rule-based approach to minimize failures in design • Add rules � Rule deck size and complexity are exploding • Make rules more strict � Highly conservative rules prevent benefits of advanced processes • Add margin � Compounding effect of margin + margin + margin • Drawbacks – Sacrifice performance – Increase area +/or power – Lengthen design cycle – Miss unanticipated interactions between effects February 16, 2007 Cadence Confidential: Cadence Internal Use Only 10

Design rules are a tradeoff Design Speed vs. Rule effectiveness Set • To make rules execute fast, keep them simple • To make simple rules effective, Yield be conservative and add margin weak � Design Constraints � strict February 16, 2007 Cadence Confidential: Cadence Internal Use Only 11

Current approach: recommended rules Recommended Required Rules Rules Recommended rules are: • More strict • More complex • More run time • Optional Yield weak � Design Constraints � strict February 16, 2007 Cadence Confidential: Cadence Internal Use Only 12

More Rules – Recommended Rules – Don’t Solve the Problems • Still have too many rules, too-strict rules, too much margin • Rules don’t handle interaction of effects – multivariate correlations – Litho stepper shallow depth of focus ↔ uneven chip surface from CMP – OPC on adjacent DRC-clean shapes produces artifacts (extra shapes) – Multiple DRC-clean layers stack up to allow soft spot for CMP erosion • Rules always compromise between Type I and Type II errors – Type I: missed a true problem – Type II: highlight a false alarm • Rules don’t enable intelligent risk/benefit tradeoff Bottom-Line: Required Rules vs. Recommended Rules Drive Designers Crazy!! February 16, 2007 Cadence Confidential: Cadence Internal Use Only 13

Overview: • What is DfM? • Why DfM? – The realities below 130nm – Yield / Cost Analysis – Rules and Models • When is it going to be needed? • How is it going to be solved? – Novel approaches in design implementation • Observations and Predictions February 16, 2007 Cadence Confidential: Cadence Internal Use Only 14

Parametric Yield Very Sensitive to Litho Process Variations 65 nm L cd • For a 2-input NAND Gate: a change in Poly Gate Length of 10% – � 20% in delay variations (65 NM) – � 100% in leakage (90 NM). 90 • Width and length variation can 80 Leakage Current (pA) be predicted by using Model ±100% 70 I sub Based Lithography Analysis: 60 50 – At the Library Design level 40 – At the chip level 30 0.16 0.17 0.18 0.19 0.20 Drawn G ate Length (um ) ±10% L February 16, 2007 Cadence Confidential: Cadence Internal Use Only 15

Interconnect Variations – The Z axis Cu loss due to 130nm > 90nm > 65nm dishing (or erosion) Narrower Lines Mean Larger Impact on Electrical Parameters Decreasing Cross-Sectional Area of Line Additional Metal Layers Compound the Topographical Impact February 16, 2007 Cadence Confidential: Cadence Internal Use Only 16

Parametric Yield Very Sensitive to CMP Process Variations 1.091 1.091 1.068 1.068 1.045 1.045 1.023 1.023 45.0% 1.000 1.000 40.0% 0.977 0.977 35.0% 30.0% Nets (%) 0.955 0.955 25.0% 20.0% 15.0% 10.0% 5.0% 0.0% Setup Hold 0 1 2 3 4 5 6 7 8 9 10 11 12 Rule Model Rule Model Cap Delta (%) Path1 OK 8ps worse Path2 OK 15ps worse Path3 Minor OK RC Variation Path4 Minor 5ps better 0.977 0.977 0.977 1.000 1.000 1.000 0.955 0.955 0.955 1.022 1.022 1.022 1.045 1.045 1.045 1.068 1.068 1.068 1.091 1.091 1.091 Thickness Variation Timing Variation Joint paper “ Incorporation of CMP Modeling in RC Extraction and Timing Flow” by H. Liao, L. Song, N. Jakatdar, R. Radojcic) submitted to DAC February 16, 2007 Cadence Confidential: Cadence Internal Use Only 17

Manufacturing effects interact (2) CMP produces big variations in surface height Common process window Litho effect + CMP effect = distorted / missing feature DoF: +/- 100nm � yield failure February 16, 2007 Cadence Confidential: Cadence Internal Use Only 18

Impact of Systematic Interconnect Variations @ 65nm February 16, 2007 Cadence Confidential: Cadence Internal Use Only 19

Overview: • What is DfM? • Why DfM? – The realities below 130nm – Yield / Cost Analysis – Rules and Models • When is it going to be needed? • How is it going to be solved? – Novel approaches in design implementation • Observations and Predictions February 16, 2007 Cadence Confidential: Cadence Internal Use Only 20

Physical Effects Connect Core to Adjacency Digital SoC Custom P+R Layout Design Design Layout Optimization CORE Parasitic Extraction Design Methods LVS/DRC Litho CMP Etch “Golden” “Golden” GDS “Golden” GDS GDS Sign-Off PV Batch RET Treatment Mask / Mfrg Mask / Mfrg Verification (OPC, CMP …) “Post Design” ADJACENCY Yield Ramp and FA Industry Structure February 16, 2007 Cadence Confidential: Cadence Internal Use Only 21

Model Based Design & Abstraction Links Implementation to Manufacturing Digital SoC Custom Electrical Analysis P+R Layout Physical Analysis RLC Design Layout Optimization Parasitic Extraction LVS/DRC Litho CMP Etch “Golde n” “Golden” GDS GDS Sign-Off PV Batch RET Treatment Mask / Mfrg Verification (OPC, CMP …) Yield Ramp and FA Industry Structure February 16, 2007 Cadence Confidential: Cadence Internal Use Only 22

Context-based, Adaptive Model Resolution • In the Design • In the Flow – Increased model – Adaptive model resolution resolution for optimizing and speed-accuracy trade- critical and sensitive paths off to match abstraction level RTL Model Resolution Synthesis Prototyping Physical Synthesis Routing Nets/Paths Optimization Sign-off Regions February 16, 2007 Cadence Confidential: Cadence Internal Use Only 23