THE WHOLE TAMALE
Mostly
THE WHOLE TAMALE Mostly ASSEMBLY/MEMORY IMAGE # Execution begins - - PowerPoint PPT Presentation
THE WHOLE TAMALE Mostly ASSEMBLY/MEMORY IMAGE # Execution begins at address 0 Process-specific data ! .pos 0 irmovq stack, %rsp # Set up stack pointer structures ! rrmovq %rsp, %rbp # initialize the base pointer Different for (e.g.,
Mostly
# Execution begins at address 0 .pos 0 irmovq stack, %rsp # Set up stack pointer rrmovq %rsp, %rbp # initialize the base pointer call main # Execute main program halt # Terminate program # Array of 4 elements .align 8 array: .quad 0x000d000d000d .quad 0x00c000c000c0 .quad 0x0b000b000b00 .quad 0xa000a000a000 main: pushq %rbp rrmovq %rsp, %rbp irmovq array,%rdi irmovq $4,%rsi call sum # sum(array, 2) ret # long sum(long *start, long count) # start in %rdi, count in %rsi sum: pushq %rbp rrmovq %rsp, %rbp irmovq $8,%r8 # Constant 8 irmovq $1,%r9 # Constant 1 xorq %rax,%rax # sum = 0 andq %rsi,%rsi # Set CC jmp test # Goto test loop: mrmovq (%rdi),%r10 # Get *start addq %r10,%rax # Add to sum addq %r8,%rdi # start++ subq %r9,%rsi # count--. Set CC test: jne loop # Stop when 0 ret # Return # Stack starts here and grows to lower addresses .pos 0xf8 stack:
Kernel code and data! Memory mapped region ! for shared libraries! Runtime heap (via malloc)! Code (.text)! Initialized data (.data)! Uninitialized data (.bss)! User stack!
0!
%rsp Process! virtual! memory! brk Physical memory! Identical for each process ! Process-specific data! structures ! (e.g., page tables,! task and mm structs, kernel! stack)! Kernel! virtual ! memory!
0x400000!
Different for each process !
# Execution begins at address 0 .pos 0 irmovq stack, %rsp # Set up stack pointer rrmovq %rsp, %rbp # initialize the base pointer call main # Execute main program halt # Terminate program # Array of 4 elements .align 8 array: .quad 0x000d000d000d .quad 0x00c000c000c0 .quad 0x0b000b000b00 .quad 0xa000a000a000 main: pushq %rbp rrmovq %rsp, %rbp irmovq array,%rdi irmovq $4,%rsi call sum # sum(array, 2) ret # long sum(long *start, long count) # start in %rdi, count in %rsi sum: pushq %rbp rrmovq %rsp, %rbp irmovq $8,%r8 # Constant 8 irmovq $1,%r9 # Constant 1 xorq %rax,%rax # sum = 0 andq %rsi,%rsi # Set CC jmp test # Goto test loop: mrmovq (%rdi),%r10 # Get *start addq %r10,%rax # Add to sum addq %r8,%rdi # start++ subq %r9,%rsi # count--. Set CC test: jne loop # Stop when 0 ret # Return # Stack starts here and grows to lower addresses .pos 0xf8 stack:
Kernel code and data! Memory mapped region ! for shared libraries! Runtime heap (via malloc)! Code (.text)! Initialized data (.data)! Uninitialized data (.bss)! User stack!
0!
%rsp Process! virtual! memory! brk Physical memory! Identical for each process ! Process-specific data! structures ! (e.g., page tables,! task and mm structs, kernel! stack)! Kernel! virtual ! memory!
0x400000!
Different for each process !
Main! memory! I/O ! bridge! Bus interface! ALU! Register file! CPU! System bus! Memory bus! Host bus ! adapter ! (SCSI/SATA)! Graphics! adapter! USB! controller! Mouse! Key! board! Monitor! I/O bus! Expansion slots for!
as network adapters! ! Disk ! controller! Disk drive! Solid ! state ! disk!
Control Signals Processor State Signals
Z S O
IR
pewpcr irw maw mew mdr rw rr rd rs aw alu cw cr
16
PC
E
pcw
SEL E
pcr
IR
E
irw
MA
E
maw
MD
E
mdw
SELE
mdr
Main Memory R0
E
R1
E
R2
E
R3
E
MUX
E S I0 I1 I2 I3 Out 16 16
SELECT
E S O0 O1 O2 O3
rw rr rd rs
A
E A B C ALU
aw alu
2 16 16
C
E
cw
SEL E
cr
Z S O
16 16 2 2
time RTN alu rd rs rw rr aw cw cr pcr pcw maw mdr mdw irw 0: MA←PC; C←PC+2 11 00 00 0 0 0 1 0 1 0 1 0 0 0 1: MD←M[MA]; PC←C 00 00 00 0 0 0 0 1 0 1 0 0 0 0 2: IR←MD 00 00 00 0 0 0 0 0 0 0 0 1 0 1 3: A←R[src] 00 00 01 0 1 1 0 0 0 0 0 0 0 0 4: C←A+R[r1] 00 00 10 0 1 0 1 0 0 0 0 0 0 0 5: R[r2]←C 00 10 00 1 0 0 0 1 0 0 0 0 0 0
time RTN
16
PC
E
pcw
SEL E
pcr
IR
E
irw
MA
E
maw
MD
E
mdw
SELE
mdr
Main Memory R0
E
R1
E
R2
E
R3
E
MUX
E S I0 I1 I2 I3 Out 16 16
SELECT
E S O0 O1 O2 O3
rw rr rd rs
A
E A B C ALU
aw alu
2 16 16
C
E
cw
SEL E
cr
Z S O
16 16 2 2
time RTN 0: MA←PC; C←PC+2 1: MD←M[MA]; PC←C 2: IR←MD
time RTN 0: MA←PC; C←PC+2 1: MD←M[MA]; PC←C 2: IR←MD 3: A←R[r3] 4: C←A + R[r2] 5: MA←C 6: MD←M[MA] 7: A←MD
time RTN 0: MA←PC; C←PC+2 1: MD←M[MA]; PC←C 2: IR←MD 3: A←R[r3] 4: C←A + R[r2] 5: MA←C 6: MD←M[MA] 7: A←MD 8: MA←R[r1] 9: MD←M[MA] 10: C←A + MD
time RTN 0: MA←PC; C←PC+2 1: MD←M[MA]; PC←C 2: IR←MD 3: A←R[r3] 4: C←A + R[r2] 5: MA←C 6: MD←M[MA] 7: A←MD 8: MA←R[r1] 9: MD←M[MA] 10: C←A + MD 11: MD←C 12: A←R[r3] 13: C←A + R[r2] 14: MA←C 15: M[MA]←MD
Main! memory! I/O ! bridge! Bus interface! ALU! Register file! CPU! System bus! Memory bus! Host bus ! adapter ! (SCSI/SATA)! Graphics! adapter! USB! controller! Mouse! Key! board! Monitor! I/O bus! Expansion slots for!
as network adapters! ! Disk ! controller! Disk drive! Solid ! state ! disk!
Regs! L1 ! d-cache! L1 ! i-cache! L2 unified cache ! Core 0! Regs! L1 ! d-cache! L1 ! i-cache! L2 unified cache ! Core 3!
…!
L3 unified cache ! (shared by all cores) ! Main memory ! Processor package!
int sumarraycols(int a[M][N]) { int i, j, sum = 0; for (j = 0; j < N; j++) for (i = 0; i < N; i++) sum += a[i][j]; }
Regs! L1 cache ! (SRAM)! Main memory! (DRAM)! Local secondary storage! (local disks)!
Larger, ! slower, ! and ! cheaper ! (per byte)! storage! devices!
Remote secondary storage! (distributed file systems, Web servers)!
Local disks hold files retrieved from disks on remote network servers.! Main memory holds disk ! blocks retrieved from local ! disks.!
L2 cache ! (SRAM)!
L1 cache holds cache lines retrieved from the L2 cache.! CPU registers hold words retrieved from cache memory.! L2 cache holds cache lines! retrieved from L3 cache!
L0:! L1:! L2:! L3:! L4:! L5:!
Smaller,! faster,! and ! costlier! (per byte)! storage ! devices!
L3 cache ! (SRAM)!
L3 cache holds cache lines! retrieved from memory.!
L6:!
Spatial Locality, or the fact that when a given address has been referenced, it is likely that addresses near it will be referenced within a short period of time. Temporal Locality,
particular memory item has been referenced, it is likely that it will be referenced again within a short period of time.
# Execution begins at address 0 .pos 0 irmovq stack, %rsp # Set up stack pointer rrmovq %rsp, %rbp # initialize the base pointer call main # Execute main program halt # Terminate program # Array of 4 elements .align 8 array: .quad 0x000d000d000d .quad 0x00c000c000c0 .quad 0x0b000b000b00 .quad 0xa000a000a000 main: pushq %rbp rrmovq %rsp, %rbp irmovq array,%rdi irmovq $4,%rsi call sum # sum(array, 2) ret # long sum(long *start, long count) # start in %rdi, count in %rsi sum: pushq %rbp rrmovq %rsp, %rbp irmovq $8,%r8 # Constant 8 irmovq $1,%r9 # Constant 1 xorq %rax,%rax # sum = 0 andq %rsi,%rsi # Set CC jmp test # Goto test loop: mrmovq (%rdi),%r10 # Get *start addq %r10,%rax # Add to sum addq %r8,%rdi # start++ subq %r9,%rsi # count--. Set CC test: jne loop # Stop when 0 ret # Return # Stack starts here and grows to lower addresses .pos 0xf8 stack:
9 1 1 30 1 1 1 1 1 2 255 1 2 255 257 258 511 256 513 514 767 512 2305 7681 7681 7680 7937 7938 8191 7936 1 2 255 1 2 31 30 9
Group #: Tag #: Main Memory block numbers
Memory Address:
5 8 3 Tag Group Byte
One Cache line, 8 bytes Tag field, 5 bits Tag Memory Valid Bits Cache Memory
Main! memory! I/O ! bridge! Bus interface! ALU! Register file! CPU! System bus! Memory bus! Host bus ! adapter ! (SCSI/SATA)! Graphics! adapter! USB! controller! Mouse! Key! board! Monitor! I/O bus! Expansion slots for!
as network adapters! ! Disk ! controller! Disk drive! Solid ! state ! disk!
MMU! Physical! address! (PA)!
...!
0:! 1:! M-1:! Main memory! Virtual! address! (VA)! CPU! 2:! 3:! 4:! 5:! 6:! 7:! 4100 Data word! 4 CPU chip! Address! translation!
Address space an ordered set of non-negative integer addresses. {0, 1, 2, ...} Virtual address space is N = 2n address. {0, 1, 2, ..., N − 1} Physical address space is M = 2m address. {0, 1, 2, ..., M − 1}
Address space an ordered set of non-negative integer addresses. {0, 1, 2, ...} Virtual address space is N = 2n address. {0, 1, 2, ..., N − 1} Physical address space is M = 2m address. {0, 1, 2, ..., M − 1}
PP 2m-p-1! Physical memory!
Empty! Empty! Uncached!
VP 0! VP 1! VP 2n-p-1! Virtual memory!
Unallocated! Cached! Uncached! Unallocated! Cached! Uncached!
PP 0! PP 1!
Empty! Cached!
0! N-1! M-1! 0!
Virtual pages (VP's) ! stored on disk! Physical pages (PP's) ! cached in DRAM!
null! null!
Memory resident! page table! (DRAM)! Physical memory! (DRAM)!
VP 7! VP 4!
Virtual memory! (disk)! Valid!
0! 1! 0! 1! 0! 1! 0! 1!
Physical page! number or ! disk address! PTE 0! PTE 7! PP 0!
VP 2! VP 1!
PP 3!
VP 1! VP 2! VP 4! VP 6! VP 7!
Virtual address!
VP 3!
null! null!
Memory resident! page table! (DRAM)! Physical memory! (DRAM)!
VP 7! VP 3!
Virtual memory! (disk)! Valid!
0! 1! 1! 0! 0! 1! 0! 1!
Physical page! number or ! disk address! PTE 0! PTE 7! PP 0!
VP 2! VP 1!
PP 3!
VP 1! VP 2! VP 4! VP 6! VP 7!
Virtual address!
VP 3!
null! null!
Memory resident! page table! (DRAM)! Physical memory! (DRAM)!
VP 7! VP 4!
Virtual memory! (disk)! Valid!
0! 1! 0! 1! 0! 1! 0! 1!
Physical page! number or ! disk address! PTE 0! PTE 7! PP 0!
VP 2! VP 1!
PP 3!
VP 1! VP 2! VP 4! VP 6! VP 7!
Virtual address!
VP 3! null! null!
Memory resident! page table! (DRAM)! Physical memory! (DRAM)!
VP 7! VP 4!
Virtual memory! (disk)! Valid!
0! 1! 0! 1! 0! 1! 0! 1!
Physical page! number or ! disk address! PTE 0! PTE 7! PP 0!
VP 2! VP 1!
PP 3!
VP 1! VP 2! VP 4! VP 6! VP 7!
Virtual address!
VP 3!
null!
Memory resident! page table! (DRAM)! Physical memory! (DRAM)!
VP 7! VP 3!
Virtual memory! (disk)! Valid!
0! 1! 1! 0! 0! 1! 0! 1!
Physical page! number or ! disk address! PTE 0! PTE 7! PP 0!
VP 2! VP 1!
PP 3!
VP 1! VP 2! VP 4! VP 6! VP 7! VP 3! VP 5!
Shared!
Physical! memory! Process 1! virtual memory! Process 2! virtual memory!
Virtual page number (VPN)! Virtual page offset (VPO)! VIRTUAL ADDRESS! Physical page number (PPN)! PHYSICAL ADDRESS!
0! p–1! p! m–1! n–1! 0! p–1! p!
Page table ! base register ! (PTBR) ! If valid=0! then page! not in memory! (page fault)! Valid! Physical page number (PPN)! The VPN acts as index into the page table! Page! table! Physical page offset (PPO)!
MMU! Physical! address! (PA)!
...!
0:! 1:! M-1:! Main memory! Virtual! address! (VA)! CPU! 2:! 3:! 4:! 5:! 6:! 7:! 4100 Data word! 4 CPU chip! Address! translation!
Level 1! page table!
...!
Level 2! page tables!
VP 0! ...! VP 1023! VP 1024! ...! VP 2047! Gap!
0!
PTE 0! ...! PTE 1023! PTE 0! ...! PTE 1023! 1023 null! PTEs! PTE 1023! 1023 ! unallocated! pages! VP 9215!
Virtual! memory!
(1K - 9)! null PTEs ! PTE 0! PTE 1! PTE 2 (null)! PTE 3 (null)! PTE 4 (null)! PTE 5 (null)! PTE 6 (null)! PTE 7 (null)! PTE 8! 2K allocated VM pages! for code and data! 6K unallocated VM pages! 1023 unallocated pages! 1 allocated VM page! for the stack!
VPN 1!
0! p-1! n-1!
VPO! VPN 2! ...! VPN k!
PPN!
0! p-1! m-1!
PPO! PPN! VIRTUAL ADDRESS! PHYSICAL ADDRESS! ...! ...!
Level 1! page table! Level 2! page table! Level k! page table!
VA! Processor! Trans-! lation! Cache/! memory! PA! Data! CPU chip! TLB! VPN! PTE!
1! 2! 3! 4! 5!
VA! Processor! Trans-! lation! Cache/! memory! PTEA! Data! CPU chip! TLB! VPN! PTE! PA!
1! 2! 3! 4! 5! 6!
TLB tag (TLBT)! TLB index (TLBI)!
0! p-1! p! n-1!
VPO! VPN!
p+t-1! p+t!
L1 d-cache! 32 KB, 8-way! L2 unified cache ! 256 KB, 8-way ! L3 unified cache ! 8 MB, 16-way ! (shared by all cores) ! Main memory ! Registers! L1 d-TLB! 64 entries, 4-way! L1 i-TLB! 128 entries, 4-way! L2 unified TLB! 512 entries, 4-way! L1 i-cache! 32 KB, 8-way! MMU ! (addr translation)! Instruction! fetch! Core x4! DDR3 Memory controller ! (shared by all cores) ! Processor package! QuickPath interconnect ! To other ! cores! To I/O! bridge!
CR3! Physical ! address!
Physical ! address!
9!
VPO!
9! 12!
Virtual ! address!
L4 PT! Page ! table! L4 PTE! PPN! PPO!
40! 12!
Physical ! address!
Offset into ! physical and ! virtual page! VPN 3! VPN 4! VPN 2! VPN 1! L3 PT! Page middle! directory! L3 PTE! L2 PT! Page upper! directory! L2 PTE! L1 PT! Page global! directory! L1 PTE!
9! 9! 40!
/!
40!
/!
40!
/!
40!
/!
40!
/!
12!
/!
9!
/!
9!
/!
9!
/!
9!
/!
512 GB ! region ! per entry ! 1 GB ! region ! per entry ! 2 MB ! region ! per entry ! 4 KB ! region ! per entry !
CPU!
VPN! VPO!
36! 12!
TLBT! TLBI!
4! 32!
...!
L1 TLB (16 sets, 4 entries/set)!
VPN1!VPN2!
9! 9!
PTE!
CR3 ! PPN! PPO!
40! 12!
Page tables! TLB! miss! TLB! hit! Physical! address ! (PA)!
Result!
32/64!
...!
CT! CO!
40! 6!
CI!
6!
L2, L3, and ! main memory! L1 d-cache ! (64 sets, 8 lines/set) ! L1! hit! L1! miss! Virtual address (VA)!
VPN3!VPN4!
9! 9!
PTE! PTE! PTE!
Kernel code and data! Memory mapped region ! for shared libraries! Runtime heap (via malloc)! Code (.text)! Initialized data (.data)! Uninitialized data (.bss)! User stack!
0!
%rsp Process! virtual! memory! brk Physical memory! Identical for each process ! Process-specific data! structures ! (e.g., page tables,! task and mm structs, kernel! stack)! Kernel! virtual ! memory!
0x400000!
Different for each process ! vm_next vm_next
task_struct mm_struct
pgd mm mmap
vm_area_struct
vm_end vm_prot vm_start vm_end vm_prot vm_start vm_end vm_prot vm_next vm_start Code! Data! Shared libraries! 0! vm_flags vm_flags vm_flags
Process virtual memory!
Kernel code and data! Memory mapped region ! for shared libraries! Runtime heap (via malloc)! Code (.text)! Initialized data (.data)! Uninitialized data (.bss)! User stack!
0!
%rsp Process! virtual! memory! brk Physical memory! Identical for each process ! Process-specific data! structures ! (e.g., page tables,! task and mm structs, kernel! stack)! Kernel! virtual ! memory!
0x400000!
Different for each process !
vm_area_struct
vm_end r/o vm_next vm_start vm_end r/w vm_next vm_start vm_end r/o vm_next vm_start
Process virtual memory!
Code! Data! Shared libraries! 0! Normal page fault! Segmentation fault:! accessing a non-existing page! 1! 2! 3! Protection exception:! e.g., violating permissions by! writing to a read-only page!
13 12 11 10 9 8 7 6 5 4 3 2 1 11 10 9 8 7 6 5 4 3 2 1
VPO PPO PPN VPN (Virtual Page Number) (Virtual Page Offset) (Physical Page Number) (Physical Page Offset)
VPN PPN Valid VPN PPN Valid 28 1 8 13 1 1 – 9 17 1 2 33 1 0A 9 1 3 2 1 0B – 4 – 0C – 5 16 1 0D 2D 1 6 – 0E 11 1 7 – 0F 0D 1
13 12 11 10 9 8 7 6 5 4 3 2 1
VPO VPN
TLBI TLBT
Set Tag PPN Valid Tag PPN Valid Tag PPN Valid Tag PPN Valid 3 – 9 0D 1 – 7 2 1 1 3 2D 1 2 – 4 – 0A – 2 2 – 8 – 6 – 3 – 3 7 – 3 0D 1 0A 34 1 2 –
11 10 9 8 7 6 5 4 3 2 1
PPO PPN
CO CI CT
Idx Tag Valid B0 B1 B2 B3 Idx Tag Valid B0 B1 B2 B3 19 1 99 11 23 11 8 24 1 3A 51 89 1 15 – – – – 9 2D – – – – 2 1B 1 2 4 8 A 2D 1 93 15 DA 3B 3 36 – – – – B 0B – – – – 4 32 1 43 6D 8F 9 C 12 – – – – 5 0D 1 36 72 F0 1D D 16 1 4 96 34 15 6 31 – – – – E 13 1 83 77 1B D3 7 16 1 11 C2 DF 3 F 14 – – – –
VPN ___ TLBI ___ TLBT ____ TLB Hit? __ Page Fault? __ PPN: ____ Offset ___ CI___ CT ____ Hit? __ Byte: ____
13 12 11 10 9 8 7 6 5 4 3 2 1
VPO VPN
TLBI TLBT
11 10 9 8 7 6 5 4 3 2 1
PPO PPN
CO CI CT
VPN ___ TLBI ___ TLBT ____ TLB Hit? __ Page Fault? __ PPN: ____ Offset ___ CI___ CT ____ Hit? __ Byte: ____
13 12 11 10 9 8 7 6 5 4 3 2 1
VPO VPN
TLBI TLBT
11 10 9 8 7 6 5 4 3 2 1
PPO PPN
CO CI CT
VPN 0x0F TLBI 0x3 TLBT 0x3 TLB Hit? __ Page Fault? __ PPN: ____ Offset ___ CI___ CT ____ Hit? __ Byte: ____
13 12 11 10 9 8 7 6 5 4 3 2 1
VPO VPN
TLBI TLBT
11 10 9 8 7 6 5 4 3 2 1
PPO PPN
CO CI CT
VPN 0x0F TLBI 0x3 TLBT 0x3 TLB Hit? Y Page Fault? N PPN: 0x0D Offset ___ CI___ CT ____ Hit? __ Byte: ____
13 12 11 10 9 8 7 6 5 4 3 2 1
VPO VPN
TLBI TLBT
11 10 9 8 7 6 5 4 3 2 1
PPO PPN
CO CI CT
VPN 0x0F TLBI 0x3 TLBT 0x3 TLB Hit? Y Page Fault? N PPN: 0x0D Offset ___ CI___ CT ____ Hit? __ Byte: ____
13 12 11 10 9 8 7 6 5 4 3 2 1
VPO VPN
TLBI TLBT
11 10 9 8 7 6 5 4 3 2 1
PPO PPN
CO CI CT
VPN 0x0F TLBI 0x3 TLBT 0x3 TLB Hit? Y Page Fault? N PPN: 0x0D Offset 0x0 CI 0x5 CT 0x0D Hit? __ Byte: ____
13 12 11 10 9 8 7 6 5 4 3 2 1
VPO VPN
TLBI TLBT
11 10 9 8 7 6 5 4 3 2 1
PPO PPN
CO CI CT
VPN 0x0F TLBI 0x3 TLBT 0x3 TLB Hit? Y Page Fault? N PPN: 0x0D Offset 0x0 CI 0x5 CT 0x0D Hit? Y Byte: 0x36
13 12 11 10 9 8 7 6 5 4 3 2 1
VPO VPN
TLBI TLBT
11 10 9 8 7 6 5 4 3 2 1
PPO PPN
CO CI CT
VPN ___ TLBI ___ TLBT ____ TLB Hit? __ Page Fault? __ PPN: ____ Offset ___ CI___ CT ____ Hit? __ Byte: ____
13 12 11 10 9 8 7 6 5 4 3 2 1
VPO VPN
TLBI TLBT
11 10 9 8 7 6 5 4 3 2 1
PPO PPN
CO CI CT
VPN ___ TLBI ___ TLBT ____ TLB Hit? __ Page Fault? __ PPN: ____ Offset ___ CI___ CT ____ Hit? __ Byte: ____
13 12 11 10 9 8 7 6 5 4 3 2 1
VPO VPN
TLBI TLBT
11 10 9 8 7 6 5 4 3 2 1
PPO PPN
CO CI CT
VPN 0x0E TLBI 0x2 TLBT 0x3 TLB Hit? __ Page Fault? __ PPN: ____ Offset ___ CI___ CT ____ Hit? __ Byte: ____
13 12 11 10 9 8 7 6 5 4 3 2 1
VPO VPN
TLBI TLBT
11 10 9 8 7 6 5 4 3 2 1
PPO PPN
CO CI CT
VPN 0x0E TLBI 0x2 TLBT 0x3 TLB Hit? N Page Fault? N PPN: 0x11 Offset ___ CI___ CT ____ Hit? __ Byte: ____
13 12 11 10 9 8 7 6 5 4 3 2 1
VPO VPN
TLBI TLBT
11 10 9 8 7 6 5 4 3 2 1
PPO PPN
CO CI CT
VPN 0x0E TLBI 0x2 TLBT 0x3 TLB Hit? N Page Fault? N PPN: 0x11 Offset ___ CI___ CT ____ Hit? __ Byte: ____
13 12 11 10 9 8 7 6 5 4 3 2 1
VPO VPN
TLBI TLBT
11 10 9 8 7 6 5 4 3 2 1
PPO PPN
CO CI CT
VPN 0x0E TLBI 0x2 TLBT 0x3 TLB Hit? N Page Fault? N PPN: 0x11 Offset 0x1 CI 0xA CT 0x11 Hit? __ Byte: ____
13 12 11 10 9 8 7 6 5 4 3 2 1
VPO VPN
TLBI TLBT
11 10 9 8 7 6 5 4 3 2 1
PPO PPN
CO CI CT
VPN 0x0E TLBI 0x2 TLBT 0x3 TLB Hit? N Page Fault? N PPN: 0x11 Offset 0x1 CI 0xA CT 0x11 Hit? N Byte: ---
13 12 11 10 9 8 7 6 5 4 3 2 1
VPO VPN
TLBI TLBT
11 10 9 8 7 6 5 4 3 2 1
PPO PPN
CO CI CT
VPN ___ TLBI ___ TLBT ____ TLB Hit? __ Page Fault? __ PPN: ____ Offset ___ CI___ CT ____ Hit? __ Byte: ____
13 12 11 10 9 8 7 6 5 4 3 2 1
VPO VPN
TLBI TLBT
11 10 9 8 7 6 5 4 3 2 1
PPO PPN
CO CI CT
VPN ___ TLBI ___ TLBT ____ TLB Hit? __ Page Fault? __ PPN: ____ Offset ___ CI___ CT ____ Hit? __ Byte: ____
13 12 11 10 9 8 7 6 5 4 3 2 1
VPO VPN
TLBI TLBT
11 10 9 8 7 6 5 4 3 2 1
PPO PPN
CO CI CT
VPN 0x01 TLBI 0x1 TLBT 0x0 TLB Hit? __ Page Fault? __ PPN: ____ Offset ___ CI___ CT ____ Hit? __ Byte: ____
13 12 11 10 9 8 7 6 5 4 3 2 1
VPO VPN
TLBI TLBT
11 10 9 8 7 6 5 4 3 2 1
PPO PPN
CO CI CT
VPN 0x01 TLBI 0x1 TLBT 0x0 TLB Hit? N Page Fault? Y PPN: ____ Offset ___ CI___ CT ____ Hit? __ Byte: ____
13 12 11 10 9 8 7 6 5 4 3 2 1
VPO VPN
TLBI TLBT
11 10 9 8 7 6 5 4 3 2 1
PPO PPN
CO CI CT