SLIDE 5 SRS Firmware development Software development
FEC Firmware development
Hardware description and verification in the System Verilog language
compactness, syntax structures → more re-usable, less error prone code the language consequently gains attention of industry →increasing maturity of the EDA tools possibility to use legacy VHDL, VERILOG modules (eg. SRS specific, open cores)
The communication between entities via standard interfaces → AMBA AXI4-Stream, AHB Automatic register generation from register map specification → IDesignSpec Adoption of the current FEC design to the above guidelines
Adrian Fiergolski The SRS in the TOTEM experiment 5