The Scalable Readout System (SRS) integration into the TOTEM - - PowerPoint PPT Presentation

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The Scalable Readout System (SRS) integration into the TOTEM - - PowerPoint PPT Presentation

SRS Firmware development Software development The Scalable Readout System (SRS) integration into the TOTEM experiment Adrian Fiergolski (Warsaw University of Technology, Poland) on behalf of the TOTEM DAQ group October 14, 2013 Adrian


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SRS Firmware development Software development

The Scalable Readout System (SRS) integration into the TOTEM experiment

Adrian Fiergolski

(Warsaw University of Technology, Poland)

  • n behalf of the TOTEM DAQ group

October 14, 2013

Adrian Fiergolski The SRS in the TOTEM experiment 1

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SRS Firmware development Software development

Current DAQ scheme

In the TOTEM standalone configuration, the VME bus bandwidth limits the trigger rate to 1kHz.

Adrian Fiergolski The SRS in the TOTEM experiment 2

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SRS Firmware development Software development

Scalable Readout System

Adrian Fiergolski The SRS in the TOTEM experiment 3

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SRS Firmware development Software development

Scalable Readout System

Adrian Fiergolski The SRS in the TOTEM experiment 4

Advantages Cost effective replacement for the currently used VME-based solution offering higher bandwidth TOTEM’s implementation will be compatible with the CMS DAQ Allow standalone runs of the TOTEM Enable hardware data filtration

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SRS Firmware development Software development

FEC Firmware development

Hardware description and verification in the System Verilog language

compactness, syntax structures → more re-usable, less error prone code the language consequently gains attention of industry →increasing maturity of the EDA tools possibility to use legacy VHDL, VERILOG modules (eg. SRS specific, open cores)

The communication between entities via standard interfaces → AMBA AXI4-Stream, AHB Automatic register generation from register map specification → IDesignSpec Adoption of the current FEC design to the above guidelines

Adrian Fiergolski The SRS in the TOTEM experiment 5

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SRS Firmware development Software development

Firmware verification

The firmware is simulated using System Verilog combined with the Universal Verification Methodology (UVM) high level of abstraction (reusable) random test vector generation (guided by constraints) coverage indicating verification progress EDA tools provide UVM libraries to test popular interfaces (eg.Ethernet, I2C) The verification of the FEC defines two kind of simulations: partial simulation →to achieve faster simulation coverage of complex modules full design

Adrian Fiergolski The SRS in the TOTEM experiment 6

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SRS Firmware development Software development

Firmware verification

Adrian Fiergolski The SRS in the TOTEM experiment 7

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SRS Firmware development Software development

SRS Readout

In order to allow efficient system testing and software migration to

  • ther platforms and frameworks, the SRS readout application has

been deployed. stand-alone, multi-thread application based on Boost C++ libraries fully portable SRS readout

Adrian Fiergolski The SRS in the TOTEM experiment 8

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SRS Firmware development Software development

Future work

Finalization of the back-pressure implementation assuring UDP packet lossless readout Full support of the DTC link as soon as a mature release will be available →in contact with maintainer A.T.Martinez Implementation of the full TTC signal distribution SRU → FECs → OptoRXs Firmware support for online data validation

Adrian Fiergolski The SRS in the TOTEM experiment 9

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SRS Firmware development Software development

Thank you for your attention.

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