the memory of a program

The memory of a program Source-code is compiled into linkable object - PDF document

The memory of a program Source-code is compiled into linkable object modules Paging and Virtual Memory Memory addresses given as relative offsets Libraries contain object modules Object modules are linked together into a Operating

  1. The memory of a program � Source-code is compiled into linkable object modules Paging and Virtual Memory Memory addresses given as relative offsets Libraries contain object modules � Object modules are linked together into a Operating Systems loadable module Leave unresolved references to dynamic libraries Spring 2004 � Loadable modules are loaded into memory and execute in a process The OS + hardware map from logical address space to physical memory OS Spring ‘04 OS Spring ‘04 Physical to logical address Swapping mapping � Every memory access is handled by the � Use secondary storage to store running memory management unit (MMU) processes Example: C = A+ B Swap-out: suspend a process, copy its memory � four memory accesses (why?) from main memory to disk � Simple scheme: Swap-in: copy a stored process from disk to main Physical addr = base register + logical addr memory and resume running state � Logical addressing allows � Logical addressing: allow swapping back to a Multiple programs to co-exist in memory different location in memory Use overlays to increase the available address space � Caution: DMA and asynchronous I/O to beyond physical limitation swapped processes must take care Use shared libraries and dynamic library loading OS Spring ‘04 OS Spring ‘04 Paging Memory management: Review � Fixed partitioning, dynamic partitioning � Process memory is divided into fixed size � Problems chunks of the same size, called pages � Pages are mapped onto frames in the Internal/external fragmentation A process can be loaded only if a contiguous main memory memory chunk is available to accommodate � Process pages can be scattered all over the process the main memory Process size is limited by the main memory size � No external fragmentation � Advantage: simplicity OS Spring ‘04 OS Spring ‘04

  2. Paging example Paging support 0 A.0 0 0 � Page table maintains mapping of process 0 --- 1 A.1 1 1 1 --- pages onto frames 2 A.2 2 2 2 --- 3 A.3 3 3 � Hardware support is needed to support Process B 4 D.0 5 D.1 Process A translation of relative addresses within a 6 D.2 7 C.0 program (logical addresses) into the 8 C.1 0 7 0 4 13 memory addresses 9 C.2 1 8 1 5 14 10 C.3 2 9 2 6 11 D.3 Free Frame List 3 10 3 11 12 D.4 4 12 13 Process C Process D 14 OS Spring ‘04 OS Spring ‘04 Hardware support Address translation � Page (frame) size is a Logical address Page # Offset Frame # Offset power of 2 with page size = 2 r , a Register Page Table Ptr logical address of l+ r Page Table bits is interpreted as a Offset tuple (l,r) Page Frame P# + l = page number, r = Frame # offset within the page � Page number is used as an index into the Program Paging Main Memory page table OS Spring ‘04 OS Spring ‘04 Virtual Memory Benefits � Paging makes virtual memory possible � More processes may be maintained in the main memory Logical to physical address mapping is dynamic Better system utilization and throughput � The process size is not restricted by the = > It is not necessary that all of the process pages be in main memory during physical memory size: the process execution memory is virtual But what is the limit anyway? � Less disk I/O to swap/load programs OS Spring ‘04 OS Spring ‘04

  3. How does this work? Page Fault Handler � CPU can execute a process as long as � Put the process into blocking state some portion of its address space is � Program disk controller to read the page mapped onto the physical memory from disk into the memory E.g., next instruction and data addresses are � Later on: I/O interrupt signals completion mapped � Resume the process � Once a reference to an unmapped page is generated ( page fault ): Page fault interrupt transfers control to the OS handler OS Spring ‘04 OS Spring ‘04 Why is this practical? Virtual memory implementation � Observation: Program branching and data � Efficient run-time address translation access patterns are not random Hardware support, control data structures � Principle of locality: program and data � Fetch policy references tend to cluster Demand paging: page is brought into the memory only when page-fault occurs = > Only a fraction of the process virtual Pre-paging: pages are brought in advance address space need to be resident to � Page replacement policy allow the process to execute for sufficiently long Which page to evict when a page fault occurs? OS Spring ‘04 OS Spring ‘04 Thrashing Address translation � A condition when the system is engaged � Virtual address is divided into page in moving pages back and forth between number and offset Virtual Address memory and disk most of the time Page Number Offset � Bad page replacement policy may result � Mapping of virtual pages onto physical in thrashing frames are facilitated by page table(s) � Programs with non-local behavior Forward-mapped page tables (FMPT) Inverted page tables (IPT) OS Spring ‘04 OS Spring ‘04

  4. Address Translation using FMPT Forward-mapped page tables (FMPT) � Page table entry Virtual address Frame Number P M Other Control Bits Page # Offset Frame # Offset (PTE) structure P: present (valid) bit Register Page Table Ptr M: modified bit Page Table Page Table � Page table is an array Offset Page Frame P# of the above + Frame # Page # Index is the virtual page number Frame # Program Paging Main Memory OS Spring ‘04 OS Spring ‘04 Handling large address spaces Multilevel FMPT � One level FMPT is not suitable for large � Use bits of the virtual address to index a virtual address spaces hierarchy of page tables 32 bit addresses, 4K (2 12 ) page size, 2 32 / 2 12 � The leaf is a regular PTE = 2 20 entries ~ 4 bytes each = > � Only the root is required to stay resident 4Mbytes resident page table per process! in main memory What about 64 bit architectures?? Other portions of the hierarchy are subject to � Solutions: paging as regular process pages multi-level FMPT Inverted page tables (IPT) OS Spring ‘04 OS Spring ‘04 Two-level FMPT Two-level FMPT page number page offset p i p 2 d 10 10 12 OS Spring ‘04 OS Spring ‘04

  5. Inverted page table (IPT) Address translation with IPT � A single table with one entry per physical � Virtual address is first indexed into the page hash anchor table (HAT) � Each entry contains the virtual address � The HAT provides a pointer to a linked currently mapped to a physical page (plus list of potential page table entries control bits) � The list is searched sequentially for the � Different processes may reference the virtual address (and ASID) match same virtual address values � If no match is found -> page fault Address space identifier (ASID) uniquely identifies the process address space OS Spring ‘04 OS Spring ‘04 Address translation with IPT Translation Lookaside Buffer (TLB) Virtual address page number offset frame number � With VM accessing a memory location register involves at least two intermediate ASID HAT memory accesses ASID page number Page table access + memory access � TLB caches recent virtual to physical + hash address mappings Frame# + ASID or TLB flash is used to enforce protection IPT base HAT base register register I PT OS Spring ‘04 OS Spring ‘04 Address translation with TLB TLB internals � TLB is associative, high speed memory Each entry is a pair (tag,value) When presented with an item it is compared to all keys simultaneously If found, the value is returned; otherwise, it is a TLB miss Expensive: number of typical TLB entries: 64-1024 Do not confuse with memory cache! OS Spring ‘04 OS Spring ‘04

  6. Bits in the PTE: Present (valid) Bits in PTE: modified, used � Present (valid) bit � Modified (dirty) bit Indicates whether the page is assigned to Indicates whether the page has been frame or not modified A reference to an invalid page generates Unmodified pages need not be written back page fault which is handled by the operating to the disk when evicted system � Used bit Indicates whether the page has been accessed recently Used by the page replacement algorithm OS Spring ‘04 OS Spring ‘04 Bits in PTE Protection with VM � Access permissions bit � Preventing processes from accessing indicates whether the page is read-only or other process pages read-write � Simple with FMPT � UNIX copy-on-write bit Load the process page table base address Set whether more than one process shares a into a register upon context switch page � ASID with IPT If one of the processes writes into the page, a separate copy must first be made for all other processes sharing the page Useful for optimizing fork() OS Spring ‘04 OS Spring ‘04 Page size considerations � Small page size better approximates locality large page tables inefficient disk transfer � Large page size internal fragmentation � Most modern architectures support a number of different page sizes � a configurable system parameter OS Spring ‘04


More recommend