The Case for Heterogeneous HTAP Raja Appuswamy, Manos - - PowerPoint PPT Presentation

The Case for Heterogeneous HTAP

Raja Appuswamy, Manos Karpathiotakis, Danica Porobic, and Anastasia Ailamaki

Data-Intensive Applications and Systems Lab

EPFL

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HTAP – the contract with the hardware

Database

Hybrid OLTP & OLAP Processing

HTAP DBMS High-throughput OLTP Low-latency OLAP Fresh data

DRAM

Core

LLC DRAM

Core Core Core Core Core Core Core

DRAM

Core

LLC DRAM

Core Core Core Core Core Core Core

Massive parallelism => high concurrency Global shared memory => data sharing System-wide coherence => synchronization

HTAP on multicores

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Necessary for current systems

Shifting hardware landscape (1): Specialization of CPUs

DRAM

Core

LLC

PCIe

DRAM

Core Core Core Core Core Core Core

DRAM

Core

LLC

PCIe

DRAM

Core Core Core Core Core Core Core

1 coherence domain

DRAM

Core

LLC

PCIe

DRAM

Core Core Core Core Core Core Core

DRAM

Core

LLC

PCIe

DRAM

Core Core Core Core Core Core Core

Multiple coherence domains Multisocket multicores Intel SCC, ARM v8, Cell SPE

CPUs: general-purpose à customizable features

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Shifting hardware landscape (2): Generalization of GPUs

2008 2010 2012 2014 2016 4 8 16 20 Normalized SGEMM/Watt UVA UM Paging UM NVLink (80-200GB/s) Pascal Maxwell Kepler Fermi Tesla Dynamic Parallelism PCIe 3.0 (16 GB/s) Programmability Interface

GPUs: Niche accelerators à general-purpose processors

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Emerging hardware: Revisiting the contract

• Homogeneous Heterogeneous parallelism
• Task-parallel CPUs
• Data-parallel GPUs
• System-wide Relaxed cache coherence
• OS (FOS), FS (Hare)
• runtimes (Cosh)
• Global shared memory
• Unified address space

CurrentEmerging hardware HTAP software

• Shared-everything OLTP: N/A
• No synch. sans coherence
• Cannot exploit heterogeneity
• HTAP across processors
• Server as distributed system
• Fails to exploit shared memory

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Clean slate redesign in order

Heterogeneous HTAP (H2TAP): Caldera

• Store data in shared memory
• Run OLTP workloads on task-parallel archipelago
• Run OLAP workloads on data-parallel archipelago

Data-parallel archipelago (OLAP) Task-parallel archipelago (OLTP)

DRAM In-memory data store Core GPU DRAM DRAM Core DRAM Core DRAM Core DRAM Core DRAM Core GPU DRAM

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Loose job-to-core assignment exploits heterogeneity

H2TAP Challenges

• Store data in shared memory
• Choose optimal data layout
• OLTP on task-parallel archipelago
• Make up for (lack of) cache coherence
• OLAP on data-parallel archipelago
• Share transactionally-consistent snapshots across processors

Data-parallel archipelago (OLAP) Task-parallel archipelago (OLTP)

DRAM In-memory data store Core GPU DRAM DRAM Core DRAM Core DRAM Core DRAM Core DRAM Core GPU DRAM

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C1 C1 C1 C2 C2 C2 C3 C3 C3

DSM page

• Need to minimize PCIe data transfer to GPU
• Data access on GPU should be sequential to enable “coalescing”
• Caldera implements NSM, DSM, and PAX

Data layout

C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4

NSM page

C1 C1 C1

PAX minipage

C2 C2 C2

PAX minipage

C3 C3 C3

PAX minipage PAXpage

PAX fits GPUs best (PCIe & coalesced accesses)

OLTP without cache coherence

• Use Data-Oriented Transaction Execution principles
• Thread-to-data assignment leads to partitioned data, metadata (2PL, index)

Thd B Thd A

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• 2. Reply(&k)
• Use explicit messaging instead of implicit latching
• Exploit shared memory by exchanging pointers instead of data

OLTP without cache coherence

• 1. Msg (lookup, k)

Thd B Thd A

• 4. Release(k)
• 3. Access *k

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Enforce coherence in software

Transactionally-consistent data sharing

• Data sharing across workloads
• Use Unified Virtual Addressing (UVA) for CPU—GPU sharing
• Consistent data sharing via hardware snapshotting (ex: Hyper)
• CUDA runtime restricts use in H2TAP context
• Caldera supports lightweight software snapshotting
• OLAP queries run on immutable snapshot
• Copy-on-write performed by update transactions

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Snapshots across GPU-CPU archipelagos

Caldera blueprint

Data-parallel archipelago GPU Task-parallel archipelago DRAM DRAM DRAM DRAM In-memory data store Core Core Scheduler Query compiler Core Query runtime Query parser & optimizer

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Determine ideal processor for query Elastic core to workload assignment OLAP on database snapshot OLTP without cache coherence Compile query to X86 or PTX code

Experiments

Setup

• Two 12-core Intel Xeon E5-2650L v3 CPUs, 256GB RAM
• GeForce GTX 980 GPU (PCIe 3.0) with 4GB memory
• TPC-C, TPC-H, YCSB in various scale factors
• Silo, MonetDB, DBMS-C

Goals

• Message passing and Software snapshotting overhead
• PAX performance compared to NSM and DSM on GPUs
• Caldera performance compared to state-of-the-art

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OLTP throughput

0.5 1 1.5 2 1 2 4 8 12 16 20 24 Throughput (MTps) # cores running TPC-C NewOrder (1WH/core) Caldera Silo

Message passing-based design scales well Better code & data locality (partitioning), no synchronization overhead

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OLAP response time (incl. data movement)

2 4 6 8 10

Caldera DBMS-C MonetDB

Execution Time (sec) TPCH SF 300 - Query 6

Bounded by PCIe bandwidth (12GB/s) Emerging interconnects (NVLink): 80-200 GB/s

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Exploits GPU parallelism Saturates PCIe b/w

Impact of snapshotting

50 100 150 200 1 2 4 8 16 32 64 100 OLTP Throughput (KTps) % records touched by OLTP q1 q1-10 9x Ideal 3.5x 2 4 6 1 2 4 8 16 32 64 100 OLAP Response Time (secs) % records touched by OLTP Ideal 2x

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Limitation: Software shadow copying imposes a high overhead Possible fix: data classification, snapshot sharing, h/w acceleration

Impact of data layout

1 table (i1 integer, i2 integer, …. i16 integer) SELECT SUM(colA + colB) FROM table

Data (16GB) in host memory Data (1GB) in GPU memory

1 2 3 4 DSM PAX NSM Execution Time (msec.) 1 2 3 DSM PAX NSM Execution Time (sec.)

PAX, DSM saturate PCIe NSM 14x worse (non-coalesced accesses) PAX exploits GPU memory BW NSM only 2x worse (GPUs have reduced the access “tax”)

Hybrid layouts like PAX a good fit for H2TAP

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Conclusion

• Hardware architecture is changing
• New opportunities: massive parallelism, fast interconnects
• New challenges: heterogeneity, relaxed coherence
• Databases can and should exploit hardware trends
• Exploit hardware heterogeneity in their core architecture design
• Decouple system-wide coherence from shared memory
• Time to move from HTAP to H2TAP
• H2TAP architecture: revisit age-old h/w—s/w contract
• Caldera: Preliminary prototype to prove that H2TAP is possible

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