Temporal Partioning Temporal - - PDF document

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26/10/2001 Reconfigurable Systems 1

ÿþýüûúùø÷öõôóþòñðïîþíï

Mikael Olausson Computer Engineering Department of Electrical Engineering Linköping University

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÷îóùûþ

Temporal Partioning Temporal Partioning with Partial Reconfiguration Embedded Reconfigurable Architectures Conclusions

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þíüöõóòõöîùîùüûùûø

• M. Kaul, R. Vemuri, ”Temporal

Partitioning Combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs”, Proc. DATE 1999 Temporal Configuration Application partitioning

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óîþöûõîùþï

Many different implementations

ÿ Area ÿ Latency

Intergrate partitioning with synthesis Iterative process

ÿ Lowest latency that meets area

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õöîùîùüûùûøòóþþóï

Behavior level Register Transfer Level Gate level

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þïùøûòüùûîï

Different implementations of the same task

ÿ Time-Area tradeoff ÿ Serial vs Parallel

Too many design points?

ÿ Candidate design points

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õûðòüöòþò õöîùîùüûùûøï

Spatial Partitioning

ÿ Increase partitioning ÿ Consumes more area ÿ Parallel processing => Less latency

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õûðòüöòþò õöîùîùüûùûøïòýüûî

Temporal Partitioning

ÿ Increase partitions ÿ Increase the available area

Will Latency decrease?

ÿ Heavily dependent on the reconfiguration

times

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õöîùîùüûùûø

• 1. Map tasks to partitions
• 2. Map each partition to several design

points

• 3. Explore multiple implementations of

the design point

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• û÷îòîüòóøüöùîí

Behavior specification(Task graph)

ÿ Tasks ÿ Communication between

Target Architecture

ÿ Area ÿ Memory size ÿ Configuration times

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þòóøüöùîí

Find the constraints

ÿ Minimum number of partitions, lower bound

Nl

min ÿ Minimum number of partitions, upper

bound Nu

min ÿ Worst case latency Dmax ÿ Best case latency Dmin

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óøüöùîíòñîþï

• 1. Find one solution for the constraints
• 2. Tighten the latency constraints
• 3. Increase the partition size and start
• ver

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ñþõöýòóùíùîï

New Dmax=(Dmax+Dmin)/2 Stop when Dmax-Dmin < δ or when no new solutions are found time limit Start and stop parameters for the partitioning search α and γ When reconfiguration time is large, set α=γ=0

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õíóþï

4x4 DCT with low reconf. Time 10ns

300 Inf 1.155 6.500 1 12 300 Inf 1.125 6.500 1 11 300 Inf 6.314 6.407 5 300 Inf 5.568 6.314 4 300 Inf 4.077 5.568 3 300 Inf 1.095 4.077 2 278.8 6.500 1.095 7.060 1 10 300 Inf 6.455 6.840 6 300 Inf 5.685 6.455 5 300 Inf 4.145 5.685 4 300 Inf 1.065 4.145 3 77.32 7.060 1.065 7.226 2 37.40 9.650 1.065 25.710 1 9 T Da Dmin Dmax Result Bounds I N

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õíóþï

4x4 DCT with high reconf. Time 30ms

300 Inf 6.956 7.244 6 281.93 7.380 6.956 7.533 5 185.73 8.100 6.956 8.111 4 78.95 9.100 6.956 9.226 3 300 Inf 795 6.956 2 77.60 9.630 795 25.440 1 9 300 Inf 795 25.440 1 8 T Da Dmin Dmax Result Bounds I N

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õöîùõóò ÿþýüûúùø÷öõîùüû

• S. Ganesan, R. Vemuri, ”An Integrated

Temporal Partitioning and Partial Reconfiguration Technique for Design Latency Improvement”, Proc. DATE 2000. One part executing, one part reconfiguring

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õöî òÿþýüûòýüûîò

TP1 TP1 TP2 TP2 TP3 TP3 TP1 TP2 TP3

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õïùýòüûýþî

For maximum overlap:

ÿ Exe(Tpi) comparable to Rec(Tpi+1) ÿ Or Exe(Tpi) >= Rec(Tpi+1)

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Input behaviour specification in C or VHDL Generate a Control Data Flow Graph(CDFG) Partioner + area estimator => Temporal segments High-level synthesis => RTL

ñðûîþïùï

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• û÷îòïþýùúùýõîùüû

BLK_1 BLK_2 BLK_3 BLK_4 Behaviour Block Intermediate Format (BBIF)

Input Set Output Set Local Set Function Graph

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õöøþîòöýùîþýî÷öþ

Xilinx 6200 FPGA

Host-side CTRL RC1 RC2 Switch between execution and reconfiguration

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üüòõöîùîùüûùûø

Entire loop in one partition Why?

ÿ Easy partioning ÿ Execution time maximum overlapped

If the loop don’t fit?

ÿ Report a failure ÿ Use the whole device(the adopted one)

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üûùîùüûõóò þþý÷îùüû

We have to wait for the

• utcome of the conditional

executing Conditional in one, branches in the other If this fails

ÿ Host polling

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óüýòöüýþïïùûø

Gives high execution times One configuration for many inputs

ÿ Filters ÿ FFT

Works only with no dependencies between inputs

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ÿþï÷óî

51.2 4.08 2088 1995.7 180 22 FR 2.0x 2.52 2.04 1991 51.47 180 48 PR DCT Speed up vs full % rec. Through- put (ms) Exe time (us) Rec. Time (us) #Inp blocks #TP Method Design 61.2 0.995 385 610 1 2 FR 1.8x 30 0.550 385 165 1 3 PR SEG Speed up vs full % rec. Through- put (ms) Exe time (us) Rec. Time (us) #Inp blocks #TP Method Design 59.5 0.26 103.1 154.8 165 2 FR 1.52x 25.7 0.21 154.7 54.03 165 3 PR 1d FFT Speed up vs full % rec. Through- put (ms) Exe time (us) Rec. Time (us) #Inp blocks #TP Method Design 98.9 0.087 0.9 86 1 1 FR 1x 98.9 0.087 0.9 86 1 1 PR TLC Speed up vs full % rec. Through- put (ms) Exe time (us) Rec. Time (us) #Inp blocks #TP Method Design

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÷þïîùüûï

? What is required for good performance? ? Would more partitions be better? ? Can parallel processing increase the

performance?

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ÿþýüûúùø÷öõôóþò öýùîþýî÷öþï

Yanbing Li, et al., ”Hardware-Software Codesign of Embedded Reconfigurable Architectures”, Proc. DAC 2000. Speed up execution with FPGA

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õöøþîòöýùîþýî÷öþ

Target Architecture

CPU FPGA Mem

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ùíôóþ

HW/SW partitioner From sytem-level described in C Loop and Basic block level Two dimensional partioning

ÿ Spatial ÿ Temporal

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ùíôóþòýüûî

Search for candidate loops for implementation i HW 1 SW loop vs. 1 or more HW loops Search for Instruction Level Paralellism

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þðòùïï÷þïòôðò õöîùîùüûùûø

Dynamic reconfiguration costs Compiler optimations(SW) HW design space Profiling information for HW/SW tradeoffs

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ÿþîöøþîõôóþòñðîþí

Yes!! Platform described in ADL by

ÿ Type of processor ÿ Characteristics of the FPGA ÿ Memory

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ðòóüüï

Significant portion of the execution time Compact implementation of loops

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öþöüýþïïùûø

Profile target architecture Extract loops Synthesize HW of loops Multiple HW structures

ÿ Loop unrolling ÿ Procedure inlining ÿ Branch trimming

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óüôõóòüïîò÷ûýîùüû

Maximize overall performance What to include?

ÿ SW execution times ÿ HW execution times ÿ Entry times for HW implementations ÿ Exit times for HW implementations ÿ Configuration times

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óøüöùîíòóü

Loop Entry Profiling(LED) Interesting Loop Detection(ILP) Intra Loop Selection Inter Loop Selection

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üüòûîöðòöüúùóùûø

Identify all loops Trace all the loop entries Compression

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• ûîþöþïîùûøòüüò

ñþóþýîùüû

Precentage contribution to application time

• óüü ï

óüü ï óüü ï óüü ï

• üîõó

üîõó üîõó üîõó òþþ òþþ òþþ òþþ îùíþ îùíþ îùíþ îùíþ

õ þóþîòùíõøþ õ þóþîòùíõøþ õ þóþîòùíõøþ õ þóþîòùíõøþ ýüí öþïïùüû ýüí öþïïùüû ýüí öþïïùüû ýüí öþïïùüû òþûýü ùûø òþûýü ùûø òþûýü ùûø òþûýü ùûø

• þýü ùûø

þýü ùûø þýü ùûø þýü ùûø òþûýü þö òþûýü þö òþûýü þö òþûýü þö ñù õý ñù õý ñù õý ñù õý þûýöð îùüû þûýöð îùüû þûýöð îùüû þûýöð îùüû 26/10/2001 Reconfigurable Systems 39

• ûîöõòüüòñþóþýîùüû

Choose the best HW solution that fits the FPGA. Execution times. Place infreq. branches in SW for too big HW solutions Keep the pure SW solution Leave configuration times out

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• ñòýüûî

Why do we leave out configuration time? The number of configurations for the loops are not available yet. We haven’t made the HW/SW partitioning yet.

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• ûîþöòüüòñþóþýîùüû

One SW and one HW solution Interactions between loops Too big search area (2n) Group loops into clusters

ÿ Competing loops

ÿ Nested loops, branches

Exhautive search within the clusters

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üòøüüòùïòîþò õóøüöùîí

8.42e+6 1.47e+7 0.28 8.57e+6 1.53 62 UNEPIC decoding 8.00e+5 1.10e+5 0.01 8.00e+4 0.04 6 Skipjack encoding 7.00e+4 8.00e+4 0.04 7.09e+4 0.08 16 ADPCM 7.17e+8 1.58e+9 0.49 7.47e+8 1.92 165 MPEG-2 encoder 1.74e+5 5.10e+5 0.05 1.74e+5 0.17 25 Wavelet compression Performance (cycles) CPU time(s) Performance (cycles) CPU time(s) Upper bound performance (cycles) Local optimization The algorithm #Loop s Benchmark 8.00e+4 8.57e+6 7.09e+4 7.47e+8 1.74e+5

8.00e+5 8.42e+6 7.00e+4 7.17e+8 1.74e+5 1.10e+5 1.47e+7 8.00e+4 1.58e+9 5.10e+5

1.10e+5 1.47e+7 8.00e+4 1.58e+9 5.10e+5

8

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÷þïîùüûï

? What is the differece between spatial

and temporal partitioning?

? How can we speed up execution even

more?

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üûýó÷ïùüûï

Partitioning in reconfigurable logic(FPGA) Spatial and Temporal partitiong Config-Exe-Recon-exe ..... Execute and reconfigure in parallel Speedup embedded CPU with HW in FPGA