TAU18 WORKSHOP MONTEREY, MARCH 15-16 2018 TOM SPYROU (INTEL) - - PowerPoint PPT Presentation

TAU’18 WORKSHOP

MONTEREY, MARCH 15-16 2018

TOM SPYROU (INTEL) – GENERAL CHAIR SONG CHEN (SYNOPSYS) – TECHNICAL PROGRAM CHAIR

First of All

THANK YOU all for registering and coming to the workshop! Your participation and contribution are critical to this event.

CALL FOR SUPPORT

• Submit papers
• TAU is a workshop, both practical application and theoretical research work are welcome
• You can still publish your paper at other conferences (DAC, ICCAD, DATE, ISPED, ISQED, etc.)
• Volunteer talks
• Share your perspectives and experiences
• Both solutions and questions
• Pose challenges and controversial topics
• Establish Network
• Connect with academia, EDA, industry: challenges, ideas, collaborations, etc.
• Academia/industry: please submit ideas/challenges and participate TAU contest!

TAU 2018 SPONSORS Thank you!

TAU 2018 PARTICIPATION

• ~38 attendees
• Academia, EDA, design houses, foundries
• UIUC, Kyoto Univ. (Japan), National Chiao Tung Univ. (Taiwan), National Tsing Hua Univ.

(Taiwan), Saitana Univ. (Tokyo), Texas A&M (Texas)

• Synopsys, Cadence, Ansys, CLK DA, Intel
• Achronix, Ansys, Broadcom, Global Foundaries, IBM, Intel, Inphy, MediaTek, Micro Sem,

Nvidia, Qualcomm, TSMC, Xilinx

TAU 2018 ORGANIZATION

Organizing Committee

• General chair: Tom Spyrou (Intel)
• TPC chair: Song Chen (Synopsys)
• Contest chair : George Chen (Intel)

Contest Committee

• Amit Dhuria (Cadence)
• Xi Chen (Synopsys)

Technical Program Committee

• Song Chen (Synopsys) - TPC chair
• George Chen (Intel) - Contest chair
• Igor Keller (Cadence)
• Christian Lutkemeyer (inPhi)
• Jeffrey Hemmett (IBM)
• João Geada (CLK DA)
• Jonathan Bishop (Mentor Graphics)
• Ken Stevens (University of Utah)
• Masanori Hashimoto (Osaka

University)

• Oleg Levitsky (Intel)
• Oscar Ou (MediaTek)
• Peng Li (Texas A&M University)
• Praveen Ghanta (Cadence)

Technical Program Committee

• Ramesh KS (Intel)
• Subra Sripada (Synopsys)
• Vladimir Zolotov (IBM)
• Kevin Chen (TSMC)
• Xin Li (Carnegie Mellon University)
• Chunyang Feng (Duke Kunshan

University)

• Praveen Ghanta (Cadence)
• Debjit Sinha (IBM)
• K.S. Ramesh (Intel)
• Kelvin Le (Cadence)
• Ken Stevens (University of Utah)

TAU 2018 PROGRAM HIGHLIGHTS

• Keynotes/Invited talks
• Variation-Tolerant Adaptive and Resilient Designs in Nanoscale CMOS – Vivek De (Intel)
• DvD impact on timing and timing optimization of power grid design – Joao Geada (Ansys)
• Software Acceleration with FPGA co-processing? – David Munday (Intel)
• Make STA Accurate and Great Again! An in depth discussion of accuracy and runtime – Igor Keller (Cadence)
• Use of Graph Databases to Aid in the Timing Analysis of the World's Fastest Microprocessors – Kerim Kalafala (IBM)
• Panels
• Aging Effects Modeling and Analysis
• Challenges & Advances in Rail Analysis and Voltage Variation Aware STA
• Contest
• Efficient generation of timing reports from an STA graph with updated arrival and required times

TAU 2018 LOGISTICS

• Amenities
• Free WIFI – access code tau18
• Reception: Today 7-9PM
• Open bar: water, soft-drinks, beer, wine, etc.
• 2 tickets/person
• Plated dinner
• Presenters
• Email slides to acmtauconference@outlook.com (directly to conference laptop)
• Can use your own computer if needed
• USB sticks