TAU18 WORKSHOP MONTEREY, MARCH 15-16 2018 TOM SPYROU (INTEL) - PowerPoint PPT Presentation

TAU’18 WORKSHOP MONTEREY, MARCH 15-16 2018 TOM SPYROU (INTEL) – GENERAL CHAIR SONG CHEN (SYNOPSYS) – TECHNICAL PROGRAM CHAIR

First of All THANK YOU all for registering and coming to the workshop! Your participation and contribution are critical to this event.

CALL FOR SUPPORT • Submit papers • TAU is a workshop, both practical application and theoretical research work are welcome • You can still publish your paper at other conferences (DAC, ICCAD, DATE, ISPED, ISQED, etc.) • Volunteer talks • Share your perspectives and experiences • Both solutions and questions • Pose challenges and controversial topics • Establish Network • Connect with academia, EDA, industry: challenges, ideas, collaborations, etc. • Academia/industry: please submit ideas/challenges and participate TAU contest!

Thank you! TAU 2018 SPONSORS

TAU 2018 PARTICIPATION • ~38 attendees • Academia, EDA, design houses, foundries • UIUC, Kyoto Univ. (Japan), National Chiao Tung Univ. (Taiwan), National Tsing Hua Univ. (Taiwan), Saitana Univ. (Tokyo), Texas A&M (Texas) • Synopsys, Cadence, Ansys, CLK DA, Intel • Achronix, Ansys, Broadcom, Global Foundaries, IBM, Intel, Inphy, MediaTek, Micro Sem, Nvidia, Qualcomm, TSMC, Xilinx

TAU 2018 ORGANIZATION Technical Program Committee Technical Program Committee Organizing Committee • • Song Chen (Synopsys) - TPC chair Ramesh KS (Intel) • General chair: Tom Spyrou (Intel) • • George Chen (Intel) - Contest chair Subra Sripada (Synopsys) • TPC chair: Song Chen (Synopsys) • • Igor Keller (Cadence) Vladimir Zolotov (IBM) • • • Contest chair : George Chen (Intel) Christian Lutkemeyer (inPhi) Kevin Chen (TSMC) • • Jeffrey Hemmett (IBM) Xin Li (Carnegie Mellon University) • • João Geada (CLK DA) Chunyang Feng (Duke Kunshan University) Contest Committee • Jonathan Bishop (Mentor Graphics) • Praveen Ghanta (Cadence) • Ken Stevens (University of Utah) • Amit Dhuria (Cadence) • Debjit Sinha (IBM) • Masanori Hashimoto (Osaka • Xi Chen (Synopsys) • University) K.S. Ramesh (Intel) • • Oleg Levitsky (Intel) Kelvin Le (Cadence) • • Oscar Ou (MediaTek) Ken Stevens (University of Utah) • Peng Li (Texas A&M University) • Praveen Ghanta (Cadence)

TAU 2018 PROGRAM HIGHLIGHTS • Keynotes/Invited talks • Variation-Tolerant Adaptive and Resilient Designs in Nanoscale CMOS – Vivek De (Intel) • DvD impact on timing and timing optimization of power grid design – Joao Geada (Ansys) • Software Acceleration with FPGA co-processing? – David Munday (Intel) • Make STA Accurate and Great Again! An in depth discussion of accuracy and runtime – Igor Keller (Cadence) • Use of Graph Databases to Aid in the Timing Analysis of the World's Fastest Microprocessors – Kerim Kalafala (IBM) • Panels • Aging Effects Modeling and Analysis • Challenges & Advances in Rail Analysis and Voltage Variation Aware STA • Contest • Efficient generation of timing reports from an STA graph with updated arrival and required times

TAU 2018 LOGISTICS • Amenities • Free WIFI – access code tau18 • Reception: Today 7-9PM • Open bar: water, soft-drinks, beer, wine, etc. • 2 tickets/person • Plated dinner • Presenters • Email slides to acmtauconference@outlook.com (directly to conference laptop) • Can use your own computer if needed • USB sticks