Shankar Balachandran* Associate Professor, CSE Department Indian Institute of Technology Madras
*Currently a Visiting Professor at IIT Bombay
Digital Circuits and Systems
Spring 2015 Week 9 Module 51
Fast Adder
Systems Fast Adder Shankar Balachandran* Associate Professor, CSE - - PowerPoint PPT Presentation
Spring 2015 Week 9 Module 51 Digital Circuits and Systems Fast Adder Shankar Balachandran* Associate Professor, CSE Department Indian Institute of Technology Madras *Currently a Visiting Professor at IIT Bombay Recursive Doubling Technique
Shankar Balachandran* Associate Professor, CSE Department Indian Institute of Technology Madras
*Currently a Visiting Professor at IIT Bombay
Fast Adder
8 7 6 5 4 3 2 1 0
Request Data From 8,7 7,6 6,5 5,4 4,3 3,2 2,1 1,0 0 From previous stages if any; This input is assumed to be stable;
Next step will have :
8,7,6,5 7,6,5,4 6,5,4,3 5,4,3,2 4,3,2,1 3,2,1,0 2,1,0 1,0 0
Next step will have :
Next step will have : 8->1 7->0 6->0 5->0 4->0 3,2,1,0 2,1,0 1,0 0
Next step will have : 8->0 7->0 6->0 5->0 4->0 3,2,1,0 2,1,0 1,0 0
High speed Addition as a circuit
A(0) B(0) A(1) B(1) A(2) B(2) A(n-1) B(n-1) S(0) C(1) S(1) C(2) S(2) C(3) S(n-1) C(n) C(n-2)
FA(0) FA(1) FA(2)
FA(n-1)
C(0)
a(j) b(j) c(j) c(j+1) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
(*)
k p g k k k g p k p g g k g g
y(j) = x(0) (*) x(1) (*) … x(j) x(0) = k If y(j) = k then c(j) = 0 If y(j) = g then c(j) = 1 Note that y(j) != p
A prefix computation
y(0) = x(0) = k y(1) = x(0) (*) x(1) y(2) = x(0) (*) x(1) (*) x(2) ……. y(n) = x(0) (*) x(1) (*) …. x(n)
(Decimal example in first few slides is for 8 nodes, this example is for 7 bits ) Stable Carry In
Stable Carry In
Stable Carry In
Fast Adders 24