[PPT] - Number representation A number can be represented in binary in many PowerPoint Presentation

SLIDE 1

Number representation

William Sandqvist william@kth.se

A number can be represented in binary in many

ways. The most common number types to be

represented are:

Integers, positive integers
ne-complement, two-complement, sign-magnitude
Decimal real numbers with a fixed range

fixed-point

Decimal real numbers

floating-point

SLIDE 2

Integers

1 1 1 1 1

Positive integers:

= 1⋅26 + 1⋅25 + 1⋅23 + 1⋅22 + 1⋅20 = 109

26 25 24 23 22 21 20

But how to represent negative numbers ???

William Sandqvist william@kth.se

SLIDE 3

Sign-magnitude

William Sandqvist william@kth.se

1 1 1 1 1

Integer:

= - (1⋅25 + 1⋅23 + 1⋅22 + 1⋅20) = - 45

S 25 24 23 22 21 20

The magnitude of the number Sign-bit Drawback:

two representations

f zero (+/-) 0

1

SLIDE 4

1-complement

William Sandqvist william@kth.se

Drawbacks:

Two zeroes (+/-) 0.
At some additions adjusting is

required.

The negative numbers are the complement of the positive numbers. Bit for bit in the positive number is inverted to get the corresponding negative.

B= bN-1 bN-2 ...b1 b0 där bi∈{ 0,1}

bN-1 bN-2 ... b1 b0

Sign Bit

SLIDE 5

2-complement

William Sandqvist william@kth.se

Representation with 2-complement

B= bN-1 bN-2 ...b1 b0 där bi∈{ 0,1}

bN-1 bN-2 ... b1 b0

Sign Bit

Decimalvalue:

D(B)= - bN-1 2N-1

+ bN-2 2N-2 + ...+ b1 21+ b0 20

This is the most common representation of signed integers.

SLIDE 6

2-complement

William Sandqvist william@kth.se

Conversion example:

B= bN-1 bN-2 ...b1 b0 där bi∈{ 0,1}

1 1

Sign Bit

Decimalvalue:

D(B)= - bN-1 2N-1

+ bN-2 2N-2 + ...+ b1 21+ b0 20

= -128 + 127 = -1

1 1 1 1 1 1

It’s alwais the biggest number that corresponds to -1.

SLIDE 7

Number conversion positive number to negative

William Sandqvist william@kth.se

01111 +15 10000 invert 10001 add one 10001

15

The Twocomplement methood

SLIDE 8

Number conversion negative number to positive

William Sandqvist william@kth.se

10001

15

01110 invert 01111 add one 01111 +15

The same procedure in both directions!

Twocomplement methood

SLIDE 9

2-complement

William Sandqvist william@kth.se

000 001 010 011 100 101 110 111

1
2
4
3

3 2 1

Computer registers are "rings". The figure shows a three-bit register. When you count with signed numbers the negative numbers, are the left half of the ring.

SLIDE 10

2-complement ”fast conversion”

William Sandqvist william@kth.se

In order to easily produce 2's complement of a

binary number, you can use the following procedure:

– Start fron the right side – Copy all bits from the binary number that is 0 and the first bit that is 1. – Invert the rest of the bits.

Exemple: 2-complement from 110 is 010

Copy Invert

SLIDE 11

Sign-extension

William Sandqvist william@kth.se

In calculations the computers often need to increase the number of digits (bits) before any calculation - how do you do it with negative numbers?

1 1 1 1 1

Integer:

= -1⋅26 + 1⋅25+1⋅23 + 1⋅22 + 1⋅20 = - 45

26 25 24 23 22 21 20

Sign bit has a negative weight

1 1 1 1 1 26 25 24 23 22 21 20 1

2n-1

1 2n-2

If you want to extend the number of digits you need to copy the sign bit to all extended bits!

1 27

SLIDE 12

Addition (BV: page 264)

William Sandqvist william@kth.se

(+5) + (+2) (+7) 0101 + 0010 0111

SLIDE 13

Addition (BV: page 264)

William Sandqvist william@kth.se

(+5) + (-2) (+3) 0101 + 1110 0011 1 1 1

ignore Carry-bit could be ignored!

SLIDE 14

Addition (BV: page 264)

William Sandqvist william@kth.se

(-5) + (-2) (-7) 1011 + 1110 1001 1 1 1

ignore Carry-bit could be ignored!

1

SLIDE 15

Overflow

William Sandqvist william@kth.se

Overflow – the sign bit is not consistent with the input numbers

(+5) + (+5) (-6) 0101 + 0101 1010 1 1

SLIDE 16

Overflow 2

William Sandqvist william@kth.se

(-5) + (-5) (+6) 1011 + 1011 0110 1 1 1 1

ignore Overflow – the sign bit is not consistent with the input numbers Carry-bit could be ignored!

SLIDE 17

Subtraction (BV: page 265)

William Sandqvist william@kth.se

How do you do the subtraction in an easy way?

(+5)

(+2)

(+3) 0101

0010

????

10 ”Borrow” one

SLIDE 18

Subtraction (BV: page 265)

William Sandqvist william@kth.se

(+5)

(+2)

(+3) 0101

0010

????

Making an addition of 2's complement instead!

0101 + 1110 0011 1 1 1

ignore Carry-bit could be ignored!

SLIDE 19

Subtraction (BV: page 265)

William Sandqvist william@kth.se

(-5)

(+2)

(-7) 1011

0010

???? 1011 + 1110 1001 1 1 1

ignore

1 Carry-bit could be ignored!

SLIDE 20

Subtraction (BV: page 265)

William Sandqvist william@kth.se

(+5)

(-2)

(+7) 1011

1110

???? 0101 + 0010 0111

SLIDE 21

Subtraction (BV: page 265)

William Sandqvist william@kth.se

(-5)

(-2)

(-3) 1011

1110

???? 1011 + 0010 1101 1

SLIDE 22

2-complement summary

William Sandqvist william@kth.se

Range: -2N-1 up to 2N-1 - 1
Negation: Invert every bit (the boolean complement),

and add 1.

Expansion of bit-length: Extend with bits at the left of the

number with the same value as the sign bit.

Overflow-rule: If two numbers with the same sign are added,

it has become overflow if the result has the opposite sign.

Subtraction rule: To subtract B from A, take the two

complement of B and add to A.

SLIDE 23

Alternative way to detect

verflow (BV: page 271)

William Sandqvist william@kth.se

Overflow because c4 and c3 are different!

(+7) + (+2) (-7) 0111 + 0010 1001 1 1 c4=0 c3=1

SLIDE 24

Alternative way to detect

verflow (BV: page 271)

William Sandqvist william@kth.se

Not Overflow because c4 and c3 are the same!

(-7) + (+2) (-5) 1001 + 0010 1011 c4=0 c3=0

SLIDE 25

Alternative way to detect

verflow (BV: page 271)

William Sandqvist william@kth.se

(+7) + (-2) (+5) 0111 + 1110 0101 1 1 c4=1 c3=1 1 1

ignore

Not Overflow because c4 and c3 are the same!

Carry-bit could be ignored!

SLIDE 26

Alternative way to detect

verflow (BV: page 271)

William Sandqvist william@kth.se

(-7) + (-2) (+7) 1001 + 1110 0111 1 c4=1 c3=0 1

ignore

Overflow because c4 and c3 are different!

Carry-bit could be ignored!

SLIDE 27

Logic to detect overflow

William Sandqvist william@kth.se

For 4-bit-number Overflow if c3 och c4 are different Otherwise, it is not overflow

Overflow = c3c

4 + c 3c4 = c3 ⊕c4

Overflow = cn−1 ⊕cn

For n-bit-number XOR

SLIDE 28

Quickie Question …

William Sandqvist william@kth.se

The number +5 is represented by 0101 if we use 4 bits. What number is equivalent to -5 if we use 8-bit two's complement representation?

a: 1111 1011 b: 1111 1010 c: 1000 0101

SLIDE 29

William Sandqvist william@kth.se

Hardware for arithmetic

SLIDE 30

Half adder

William Sandqvist william@kth.se

1 0 1 1 a b

a b c s 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0

1 1 0 1 1 a b

c = a⋅b s = a ⊕ b

a b s c

HA

a b s c

SLIDE 31

Full adder

William Sandqvist william@kth.se

1 00 01 11 10 1 ab cin

a b cin cut s 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 1

1 1 1 1 1 00 01 11 10 1 cin 1 1

cut = a b + cina + cinb s = a ⊕ b ⊕ cin FA

a b cin s cut b a cin s cut

SLIDE 32

The sum function?

1 1 00 01 11 10 1 cin

s = a ⊕ b ⊕ cin

1 1

William Sandqvist william@kth.se

SLIDE 33

Sum = Odd parity

1 1 00 01 11 10 1 ab c

a ⊕ b ⊕ c

1 1

William Sandqvist william@kth.se

0 1 1 0

XOR

a b 1 0 1

a ⊕ b

The Full Adder sum function is the "odd" parity function. This is the XOR function’s natural extension to more variables than two. Odd parity is when the number of 1’s on the inputs is an odd number.

Odd parity

SLIDE 34

Carry function?

William Sandqvist william@kth.se

1 00 01 11 10 1 1 1 1

Majority function. Output assumes same value

1/0 as a majority of the inputs. M

SLIDE 35

Full-adder with two ½ -adders

William Sandqvist william@kth.se

HA HA a b cin s cut

FA

a b cin s cut

We may also construct a full-adder with two half-adders and an OR gate. Decomposition means that you see the circuit as composed of building blocks. Such known building blocks could be used to build build entirely new systems, Composition.

≡

SLIDE 36

Full-adder ½+ ½ = 1

William Sandqvist william@kth.se

1 00 01 11 10 1 ab cin

a b cin cut s 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 1

cut = (a ⊕ b)⋅cin+ a⋅b

1 1 1 1 1 00 01 11 10 1 ab cin

s = a ⊕ b ⊕ cin

1 1 HA HA cin a b s cut a b cin

s cut

(a⊕b) can be shared for both s and cut !

(a ⊕ b)⋅cin a⋅b

SLIDE 37

Popular tattoo?

William Sandqvist william@kth.se

Tattoos are forever! Unfortunately this is not the "best" adder, not if you want fast computers. Exciting continuation of adder circuits follow ...

SLIDE 38

( Parityfunction – Three-way

light control)

1 1 00 01 11 10 1 cin

s = a ⊕ b ⊕ cin

1 1

William Sandqvist william@kth.se

Odd parity.

SLIDE 39

Three-way light control - revisited

William Sandqvist william@kth.se

Brown/Vranesic: 2.8.1

x1 x2 x3 f x1 x2 x3 f Parityfunction

Odd parity

Suppose that we need to be able to turn on / off the light from three different places.

SLIDE 40

XOR or NAND?

William Sandqvist william@kth.se

x1 x2 x3 f

x1 x2 x3

f XOR gates will be much more effective than NAND gates! The former solution was based on NAND gates.

1 1 00 01 11 10 1 1 1

f

x1 x2 x3

Udda paritet

SLIDE 41

Simpler with XOR gates

William Sandqvist william@kth.se

x1 x2 x3

f ( With NAND-gates: ) 7486 With XOR-gates:

SLIDE 42

William Sandqvist william@kth.se

SLIDE 43

( Parity check )

William Sandqvist william@kth.se

PU

1 0 1 0 1 0 1 0 1

PU

1

ALARM!? A bit modified!? Data has been disturbed! Disturbance!

0 1 1 0

Data - orginal Paritybit is added Parity Check Checks if an

dd number of

"1s” is recived – error!

1 1 1 0

?

With parity function we can check whether data has been disturbed or not. Data transmitted always have even parity!

SLIDE 44

William Sandqvist william@kth.se

SLIDE 45

More composition

William Sandqvist william@kth.se

composition can be used to construct

the n-bit adder

One need n full-adders for

constructing an n-bit adder?

SLIDE 46

Ripple-Carry Adder (RCA)

William Sandqvist william@kth.se

FA

a1 b1 cin1

FA

a0 b0 cin0 s0 s1 cut0 cut1

cut0 b1 a1 s1 cut1 cin0 b0 a0 s0 +

SLIDE 47

Ripple-Carry Adder (RCA)

William Sandqvist william@kth.se

FA

a1 b1 cin1

FA

a0 b0 cin0 s0 s1

FA

an-1 bn-1 cinn-1 sn-1 cut0 cutn-1 an-1bn-1 ... a0 b0 sn-1 ... s0 cin0 cutn-1

n-bit ADD AFA area for a Fulladder tFA delay trough a Fulladder

Timedelay from cin0 to coutn-1 is

total of n⋅tFA

Total area is n⋅AFA

SLIDE 48

Ripple-Carry Adder (RCA)

William Sandqvist william@kth.se

cin0 b0 a0 s0 b1 a1 s1

Critical path

SLIDE 49

Fulladder Carry-function

William Sandqvist william@kth.se

& & & >1 & & & &

AND-OR NAND-NAND

ANAND-NAND= 14 MOS TNAND-NAND= 3TNAND AAND-OR= 20 MOS TAND-OR= 5TNAND

SLIDE 50

XOR with NAND

& & & &

a b b a⋅

b a b a b a b a b b a a b a b b a a ⊕ = + = = + ⋅ + + ⋅ = = ⋅ ⋅ + ⋅ ⋅ ) ( ) ( ) ( ) (

William Sandqvist william@kth.se

Area: AXOR=16 MOS Delay: TXOR=3TNAND

SLIDE 51

Can we construct a faster adder?

William Sandqvist william@kth.se

The delay of a ripple adder

grows proportionally with the number of bits

For 32 bits, the delay becomes

very large

SLIDE 52

generate- och propagate- funktionerna

William Sandqvist william@kth.se

pi = xi + yi

i i i i

c p g c + =

+1

gi = xiyi

1 00 01 11 10 1 1 1 1

i i i

y x p ⊕ =

Works also! ) (

1 i i i i i i i i i i i i

y x c y x y c x c y x c + + = + + =

+ i i y

x

i

c

1 00 01 11 10 1 1 1 1

i i y

x

i

c ) (

1 i i i i i i

y x c y x c ⊕ + =

+

The Carry-chain can be described by two functions:

Generate gi ( carry-out ci+1 = 1

if gi = 1 )

Propagate pi ( carry-out ci+1 = 1

if ci = 1 and xi = 1 or yi = 1 )

SLIDE 53

Carry-look-ahead function

William Sandqvist william@kth.se

c1 = g0 + p0c0 c2 = g1 + p1c1 = g1 + p1(g0 + p0c0) = g1 + p1g0 + p1p0c0

Carry-bit c0
Carry-bit c1

Only two logic levels is needed … gi = xiyi

Propagate function from ” previous” bits can be generated in parallel

pi = xi + yi

SLIDE 54

Carry-chain in ripple-adder

William Sandqvist william@kth.se

p0

c0

g0

c1

g1 g2 p1 p2

c2 c3 OR or XOR can be used for the p function!

6 gate levels

1 # 2 # 3 # 4 # 5 # 6 # ½ + ½

SLIDE 55

Quicker implementation of the Carry-chain

William Sandqvist william@kth.se

Distributive theorem: (a+b)c = ac+bc

p0 g0 g1 p1 c0 c1 c2

2 2g

p

3 3g

p

4 4g

p

5 5g

p

6 6g

p

7 7g

p

b b b b b b b b a a a a a a a a s s s s s s s s c + =

0 G

P

8-bit adder

SLIDE 58

Hierarchical expansion (BV page 277)

William Sandqvist william@kth.se

S23-16 S15-8

Block 0 CLA Block 1 CLA Block 3 CLA

a7-0 b7-0 a15-8 b15-8

Block 2 CLA

a23-16 b23-16 a31-24 b31-24

First level four 8-bit adders with Carry lookahead Second level four Carry lookahead units

P0 G0 S7-0 P1 G1 P2 G2 P3 G3 S31-24

c8 c16 c24 c32

32-bit adder

0G

P

1 1

G P G P

1 1 2 2

G P G P G P

1 1 2 2 3 3

G P G P G P G P

c

c c c c

32-bit adder. Each block consists of a 8-bit CLA.

SLIDE 59

Hierarchical expansion

William Sandqvist william@kth.se

C8 = G0+P0c0 C16 = G1+P1G0+P1P0c0 C24 = G2+P2G1+P2P1G0+P2P1P0c0 C32 = G3+P3G2+P3P2G1+P3P2P1G0+P3P2P1P0c0 etc. More gates in sequential steps, but gates with fewer inputs can be used.

SLIDE 60

(Carry look ahead three level hierarchy)

64-bit adder

16-bit LCU 64-bit LCU

SLIDE 61

Carry-Select-Adder (CSA)

William Sandqvist william@kth.se

Idea

One divides an adder in two stages with the same

number of bits

To speed up the process so you calculate the results of

the second step in advance for the two cases

Carry-in = 0 Carry-in = 1

When the calculation of the carry bit is clear for the

first step, then we choose the result of the second step depending on carry the bit value!

SLIDE 62

8-bit Carry-Select-Adder

William Sandqvist william@kth.se

c

a b s a+b = s

1 s[3:0] s[7:4] c4 c0 a[3:0] b[3:0] a[7:4] b[7:4] c c8 Add Add Add Mux c8-high c8-low

Mux

SLIDE 63

Comparision

William Sandqvist william@kth.se

Ripple-Carry Adder

T(n)= n2.5TNAND, A = n*12.5TNAND+TXOR T(4)= 14TNAND, A(4) = 50 ANAND

Carry-Lookahead Adder (4bits)

T(4)= ~8TNAND, A(4)= 43ANAND+44ANAND= ~60ANAND

Carry-Select Adder (8 bits)

T(8)= ~(8+4)TNAND, A(8)= ~(120+20)ANAND

SLIDE 64

Which is the best adder?

There is no clear answer!

Ripple adder takes a minimum of space but is slow
Carry-look-ahead adder take much space but it is fast
Carry-select adder is a compromise

One must make a trade-off between Area and speed

William Sandqvist william@kth.se

SLIDE 65

William Sandqvist william@kth.se

SLIDE 66

Subtraction

William Sandqvist william@kth.se

Subtraction can be made by the addition

f the two complement

Invert all bits of the second operand and add one

SLIDE 67

Add/sub-unit

William Sandqvist william@kth.se

s s

1

s

n 1 –

x x

1

x

n 1 –

c

n

bit adder

y y

1

y

n 1 –

c Add

⁄

Sub control

Add/Sub = 0: Addition Add/Sub = 1: Subtraction

SLIDE 68

Arithmetic Logic Unit (ALU)

William Sandqvist william@kth.se

MUX LU AU

f0 f1 Function selection A/L f0 f1 A/L

x y

cin

ALU

A/L f1 f0 Function x+y 1 x+y+cin 1 x-y 1 1 x-y-cin 1 x or y 1 1 x and y 1 1 x xor y 1 1 1 inv x

Processors use to have an ALU, not only an adder.

SLIDE 69

Comparator

William Sandqvist william@kth.se

Comparator is implemented as a subtractioncircuit

? ? ?

SLIDE 70

Comparator

William Sandqvist william@kth.se

Comparator is implemented as a subtractioncircuit

SLIDE 71

Summary

William Sandqvist william@kth.se

Addition and subtraction of integers

Two-complement
Subtraction of a number is implemented as

addition of it’s two-complement Trade-Off: Area against Speed Different Adder-structures

Ripple-Carry Adder (RCA)
Carry-Lookahead Adder (CLA)
Carry-Select Adder (CSA)

SLIDE 72

William Sandqvist william@kth.se