System-on-Chip Design Data Flow hardware Implementa8on Hao Zheng - - PowerPoint PPT Presentation

System-on-Chip Design

Data Flow hardware Implementa8on

Hao Zheng

• Dept. Comp Sci & Eng

U of South Florida haozheng@usf.edu (813) 9744757

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Single-Rate SDF to Hardware

• Single-rate SDF: all producJon/consumpJon

rates are a fixed number = 1.

– The enJre circuit controlled by a single clock.

• ImplementaJon

– Actors -> combinaJon circuits – Queues -> wires – IniJal tokens -> registers.

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Single-Rate SDF to Hardware

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diff

1 1

sort

1 1 1 1 1 1

initial token value = a initial token value = b

• ut1 = (a > b) ? a : b;
• ut2 = (a > b) ? b : a;
• ut1 = (a !=b) ? a – b : a;
• ut2 = b;

sort diff

• Fig. 3.10 Euclid’s greatest common divisor as an SDF graph

Single-Rate SDF to Hardware

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compare 1 1 compare sub

SORT DIFF SORT DIFF REGISTER

• Fig. 3.11 Hardware implementation of euclid’s algorithm

Can lead to long combinaJon paths.

SDF HW Implementa8on

• CombinaJonal path is a sequence of actors

s.t. edges between these actors do not have iniJal token.

• CriJcal path is a combinaJonal path s.t. the

sum of latencies of all actors on that path is the longest.

• CriJcal path delay determines the clock

frequency.

– Should be minimized to increase clock speed.

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Pipelining: Break Long Comb. Paths

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c0 c1 c2 + +

• ut

in x0 x1 x2

• Fig. 3.12 SDF graph of a

simple moving-average application

• ut = x0 · c2 + x1 · c1 + x2 · c0

Pipelining: Break Long Comb. Paths

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• ut = x0 · c2 + x1 · c1 + x2 · c0

c0 c1 c2 + +

• ut

in x1 x2 x3 c2x0 c1x1 c0x2

• Fig. 3.13 Pipelining the

moving-average filter by inserting additional tokens (1)

c0 c1 c2 + +

• ut

in x2 x3 x4 c2x0 c1x2 c0x3 C0x2+c1x1 c2x1

• Fig. 3.14 Pipelining the

moving-average filter by inserting additional tokens (2)

Pipelining: Break Long Comb. Paths

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• ut = x0 · c2 + x1 · c1 + x2 · c0

Pipelining: Break Long Comb. Paths

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c0 c1 c2 + +

• ut

in x2 x3 x4 c2x0 c1x2 c0x3 C0x2+c1x1 c2x1

c0 c1 c2 + +

• ut

in

Pipelining: PiCall

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ADD IN ADD IN

!=

accumulator double-accumulator for odd/even samples

Do Not add iniJal tokens unless they can be injected by a sequence of actor firings.

Mul8-Rate Expansion (Sec. 2.5.1)

11 IN A B OUT

3 2 1 1 1 1

PASS Firing Rate 2 2 3 3

IN0 A0 IN1 A1 B0 OUT0 B1 OUT1 B2 OUT2

a b c d e f

This single-rate DFG can be mapped to HW as shown previously.

HW/SW Hybrid Implementa8on

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ctr snk 1 1

data req ack P0 P1 P2 ctr

8051 Microcontroller

FIFO

snk

Hardware Design

Interface btw. HW & CPU Interface btw. SW & CPU

Reading Guide

• SecJon 3.2 - 3.3, the CoDesign book.

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