MP System-on-Chip: MP System-on-Chip: Embedded Test, Diagnosis and - - PowerPoint PPT Presentation

MP System-on-Chip: Embedded Test, Diagnosis and Repair in Practice MP System-on-Chip: Embedded Test, Diagnosis and Repair in Practice

Yervant Zorian Virage Logic Corp

zorian@viragelogic.com

Contents Contents

Introduction SoC yield & reliability challenges Optimization loop concept Infrastructure IP & resource partitioning Examples of embedding infrastructure IP Conclusions

Introduction Introduction

Cost

reduce semiconductor fabrication cost by improving

manufacturing yield

Time-to-Volume

Short time to market and short product lifecycle faster yield optimization impacts market entry time

and bottom line

Quality

Production of high quality manufactured silicon

Deep Submicron Trends Deep Submicron Trends

Number of transistors Mixed technologies Shrinking geometries Process layers New process material High performance

Deep Submicron Impact Deep Submicron Impact

Miniaturization and High Performance result in

Finer and denser semiconductor fabrication Increased susceptiblity Increased defectivity Lower manufacturing yield and reliability

Observed as

Defect density Realistic Faults Timing problems Transient or Soft Errors

Volume Fabrication Volume Volume Fabrication Fabrication Test Assembly Packaging Test Test Assembly Assembly Packaging Packaging

Production Ramp Up Production Production Ramp Up Ramp Up

In-Field In In-

• Field

Field

IP Design IP Design IP Design Failure Analysis Failure Failure Analysis Analysis Characterization Characterization Characterization SoC Design SoC Design SoC Design

IC Realization Flow IC Realization Flow

10 20 30 40 50 60 70 80 90 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Design Production Ramp Up Volume

Yield Learning Curve Fab Yield Optimization

Yield Life Cycle Curve Yield Life Cycle Curve

Yield Assessment (%)

10 20 30 40 50 60 70 80 90 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Design Production Ramp Up Volume

New Yield Learning Curve Yield Learning Curve Design Yield Optimization Fab Yield Optimization

Yield Life Cycle Curve Yield Life Cycle Curve

Yield Assessment (%)

10 20 30 40 50 60 70 80 90 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Design Production Ramp Up Volume

New Yield Learning Curve Yield Learning Curve Design Yield Optimization Fab Yield Optimization

Yield Life Cycle Curve Yield Life Cycle Curve

Yield Assessment (%)

10 20 30 40 50 60 70 80 90 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Design Production Ramp Up Volume

New Yield Learning Curve Yield Learning Curve Design Yield Optimization Fab Yield Optimization

Yield Life Cycle Curve Yield Life Cycle Curve

Yield Assessment (%)

10 20 30 40 50 60 70 80 90 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Design Production Ramp Up Volume

New Yield Learning Curve Yield Learning Curve Design Yield Optimization Fab Yield Optimization

Yield Life Cycle Curve Yield Life Cycle Curve

Yield Assessment (%)

• 1. Yield Learning Challenge
• 1. Yield Learning Challenge

Semiconductor process evolving and introducing new material and techniques

result in new generation of yield limiting factors

Small geometries

result in devices more susceptible to systematic and random

defects and higher defect densities per layer

Increased time-to-market pressure

result in chip volume production at lower yield level

Disaggregated semiconductor industry

result in F-IP providers assuming yield optimization responsibility

Need process monitor IP and yield prediction and optimization for each new design (IP and SoC)

• 2. Embedded Memory Challenge
• 2. Embedded Memory Challenge

• 2. Embedded Memory Challenge
• 2. Embedded Memory Challenge

10 20 30 40 50 60 70 80 90 100

2.69 5.39 10.78 21.56 43.11 64.67 86.22

% Memory on die

M e m

• ry

Y ie ld (% )

Memory yield (without redundancy) Memory Yield with redundancy

3 5 11 22 43 65 86

1 Mb 2 Mb 4 Mb 8 Mb 16 Mb 24 Mb 32 Mb

Percent of Memory on die Width of die in mm 12.00 Height of die in mm 12.00 Defect density for logic in # per sq. in. 0.4 Defect density for memory in # per sq. in. 0.8 Process technology 0.13 um

3 5 11 22 43 65 86

• 3. Failure Analysis Challenge
• 3. Failure Analysis Challenge

Traditional physical failure analysis steps -

Fault localization Silicon de-processing Physical characterization and inspection

Small geometries result in –

Finding smaller more subtle defects Tighter pitches require greater spatial resolution Backside analysis due to metal layers & flip-chip

Need to gather failure data using diagnosis IP and analyze obtained data by off-chip fault localization methodologies and tools

• 4. High Performance Challenge
• 4. High Performance Challenge

Increased performance require increased accuracy for proper resolution of timing signals Semiconductor off-chip speed improved 30% per year, test accuracy improved 12% per year

Tester timing errors approaching cycle time of faster

device

Yield loss due to tester inaccuracy (extra guard-

bending performed at test stage)

Need for measuring and analyzing time specifications using embedded timing probes with high accuracy

• 5. Transient Error Challenge
• 5. Transient Error Challenge

Smaller geometries and reduced power supplies result in reduced noise margins Soft errors,timing faults, crosstalk are major signal integrity problems SoC needs self correcting, i.e. embedded robustness, engine in order to resist to this challenge

Yield Optimization Loops Yield Optimization Loops

Need for Advance yield optimization solutions Introduced at different stages of chip realization flow Yield optimization feedback loops – comprised of three steps

Detection, Analysis, Correction

Three step loops either reside completely off-chip, partially on-chip/off-chip or embedded on-chip Examples of yield optimization feedback loops

Characterization Characterization Characterization

Production Ramp Up Production Production Ramp Up Ramp Up

Volume Fabrication Volume Volume Fabrication Fabrication Test Assembly Packaging Test Test Assembly Assembly Packaging Packaging

In-Field In In-

• Field

Field

IP Design IP Design IP Design Failure Analysis Failure Failure Analysis Analysis SoC Design SoC Design SoC Design

Yield Optimization Loops Yield Optimization Loops

D

• Detection

A

• Analysis

C

• Correction

Characterization Characterization Characterization

Production Ramp Up Production Production Ramp Up Ramp Up

Volume Fabrication Volume Volume Fabrication Fabrication Test Assembly Packaging Test Test Assembly Assembly Packaging Packaging

In-Field In In-

• Field

Field

IP Design IP Design IP Design Failure Analysis Failure Failure Analysis Analysis SoC Design SoC Design SoC Design

Yield Optimization Loops Yield Optimization Loops

D

• Detection

A

• Analysis

C

• Correction

Characterization Characterization Characterization

Production Ramp Up Production Production Ramp Up Ramp Up

Volume Fabrication Volume Volume Fabrication Fabrication Test Assembly Packaging Test Test Assembly Assembly Packaging Packaging

In-Field In In-

• Field

Field

IP Design IP Design IP Design Failure Analysis Failure Failure Analysis Analysis SoC Design SoC Design SoC Design

Yield Optimization Loops Yield Optimization Loops

A

C

D

1

D

• Detection

A

• Analysis

C

• Correction

Characterization Characterization Characterization

Production Ramp Up Production Production Ramp Up Ramp Up

Volume Fabrication Volume Volume Fabrication Fabrication Test Assembly Packaging Test Test Assembly Assembly Packaging Packaging

In-Field In In-

• Field

Field

IP Design IP Design IP Design Failure Analysis Failure Failure Analysis Analysis SoC Design SoC Design SoC Design

Yield Optimization Loops Yield Optimization Loops

A

C

D

1

A

D

C

2

D

• Detection

A

• Analysis

C

• Correction

Characterization Characterization Characterization

Production Ramp Up Production Production Ramp Up Ramp Up

Volume Fabrication Volume Volume Fabrication Fabrication Test Assembly Packaging Test Test Assembly Assembly Packaging Packaging

In-Field In In-

• Field

Field

IP Design IP Design IP Design Failure Analysis Failure Failure Analysis Analysis SoC Design SoC Design SoC Design

Yield Optimization Loops Yield Optimization Loops

A

C

D

1

A

D

C

2

D A

C

3

D

• Detection

A

• Analysis

C

• Correction

Characterization Characterization Characterization

Production Ramp Up Production Production Ramp Up Ramp Up

Volume Fabrication Volume Volume Fabrication Fabrication Test Assembly Packaging Test Test Assembly Assembly Packaging Packaging

In-Field In In-

• Field

Field

IP Design IP Design IP Design Failure Analysis Failure Failure Analysis Analysis SoC Design SoC Design SoC Design

Yield Optimization Loops Yield Optimization Loops

A

C

D

1

A

D

C

2

D A

C

4

D A

C

3

D

• Detection

A

• Analysis

C

• Correction

Characterization Characterization Characterization

Production Ramp Up Production Production Ramp Up Ramp Up

Volume Fabrication Volume Volume Fabrication Fabrication Test Assembly Packaging Test Test Assembly Assembly Packaging Packaging

In-Field In In-

• Field

Field

IP Design IP Design IP Design Failure Analysis Failure Failure Analysis Analysis SoC Design SoC Design SoC Design

Yield Optimization Loops Yield Optimization Loops

A

C

D

1

A

D

C

2

C

A

D

5

D A

C

4

D A

C

3

D

• Detection

A

• Analysis

C

• Correction

Characterization Characterization Characterization

Production Ramp Up Production Production Ramp Up Ramp Up

Volume Fabrication Volume Volume Fabrication Fabrication Test Assembly Packaging Test Test Assembly Assembly Packaging Packaging

In-Field In In-

• Field

Field

IP Design IP Design IP Design Failure Analysis Failure Failure Analysis Analysis SoC Design SoC Design SoC Design

Yield Optimization Loops Yield Optimization Loops

A

C

D

1

A

D

C

2

C

A

D

5

D A

C

4

D A

C

3

D A

C

6

D

• Detection

A

• Analysis

C

• Correction

Characterization Characterization Characterization

Production Ramp Up Production Production Ramp Up Ramp Up

Volume Fabrication Volume Volume Fabrication Fabrication Test Assembly Packaging Test Test Assembly Assembly Packaging Packaging

In-Field In In-

• Field

Field

IP Design IP Design IP Design Failure Analysis Failure Failure Analysis Analysis SoC Design SoC Design SoC Design

Yield Optimization Loops Yield Optimization Loops

A

C

D

1

A

D

C

2

C

A

D

5

D A

C

4

D A

C

7

D A

C

3

D A

C

6

SoC

MPEG DRAM UDL ADC CPU DSP PCI SRAM ROM

Functional IP in SoC Functional IP in SoC

Multiple Functional IP (F-IP) types have been absorbed into single SoC design

Infrastructure IP in SoC Infrastructure IP in SoC

Transparent to normal functionality of SoC (not functional IP) Ensures manufacturability and lifetime reliability of SoC Basic types of Infrastructure IP include:

IP for process monitoring IP for testing IP for diagnosis and debug IP for repair IP for characterization & measurement IP for robustness and fault tolerance

Infrastructure IP in SoC Infrastructure IP in SoC

Infrastructure IP absorbed into Soc design

External equipments and sensors Embedded I-IP on Wafer Embedded I-IP at SoC level Embedded I-IP distributed over F-IP Embedded I-IP integrated into F-IP

Resource partitioning and I-IP at multiple levels Examples of Embedding I-IP to create YOL

D

• Detection

A

• Analysis

C

• Correction

Characterization Characterization Characterization

Production Ramp Up Production Production Ramp Up Ramp Up

Volume Fabrication Volume Volume Fabrication Fabrication Test Assembly Packaging Test Test Assembly Assembly Packaging Packaging

In-Field In In-

• Field

Field

IP Design IP Design IP Design Failure Analysis Failure Failure Analysis Analysis SoC Design SoC Design SoC Design

• 1. Embedded Process Monitor IP
• 1. Embedded Process Monitor IP

A

C

D

1

A

D

C

2

• 1. Embedded Process Monitor IP
• 1. Embedded Process Monitor IP

Passing DRC does not guarantee high yield D-component of feedback loop is I-IP

Monitor process characteristics Collect device attributes

Known as: test vehicle or test die Process Monitor IP used during process development and/or later during production Process Monitor IP may be test die (full chip), scribe

• r embedded IP in SoC

Process development I-IP

Drop-in test die with scribe

Scribe only Product die with embedded IP Test die Product Die Source HPL Technologies Source HPL Technologies

• 1. Embedding Process Monitor IP
• 1. Embedding Process Monitor IP

• 1. Embedded Process Monitoring IP
• 1. Embedded Process Monitoring IP

Use information and knowledge about process to predict yield of a given design (IP or SoC) before it is committed to silicon (A- component) Identify weekest links in design

Block, IP, layer, design structures

Yield Optimization: improve design (IP or SoC) by modifying week links at GDS level (C- component)

• 1. Using Process Monitor IP
• 1. Using Process Monitor IP

Yield Projection & Optimization

Projected Yield & Optimized Design Technology File

YLFA CAA

IP or SOC Design GDS Yield Test Chip

Experience & Test Chip IP

Test Structures YMSRAM Design Test Patterns

RFA

Critical Factors & fault densities Defect densities by layer Fab Data Analysis & Characterization

Diagnostic Knowledge base

Design Stage Design Stage Process Fab Process Fab

Density of Critical Factors

B7 B4 B1 B2 B5 B3 B6

Predicted Electrical Fault Density Pareto

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 B1 B3 B2 B5 B7 B6 B4 block D0 (faults/cm2)

Predicted Electrical Fault Density Pareto

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 B1 B3 B2 B5 B7 B6 B4 block D0 (faults/cm2)

Source HPL Technologies Source HPL Technologies

• 1. Using Process Monitor IP
• 1. Using Process Monitor IP

D

• Detection

A

• Analysis

C

• Correction

Characterization Characterization Characterization

Production Ramp Up Production Production Ramp Up Ramp Up

Volume Fabrication Volume Volume Fabrication Fabrication Test Assembly Packaging Test Test Assembly Assembly Packaging Packaging

In-Field In In-

• Field

Field

IP Design IP Design IP Design Failure Analysis Failure Failure Analysis Analysis SoC Design SoC Design SoC Design

D A

C

3

D A

C

6

• 2. Embedded Test & Repair IP
• 2. Embedded Test & Repair IP

• 2. Conventional Manuf. Repair

External Test & Repair Method Store failed bit map externally in a large capture memory Use external general purpose redundancy allocation software Blow fuses using external repair equipment High cost and silicon area

• 2. I-IP for Single Time Repair
• External Memory tester

eliminated External bit map storage eliminated External redundancy analysis software eliminated High yield achieved because of integrated solution

• Small

Capture Memory

• 2. I-IP for Multi-Time Repair

External repair equipment eliminated Overall manufacturing cost reduced Efficiency of repair increased (PVT corner conditions repaired) Efficient of area & performance improved

• 2. Distributed I-IP for ET&R
• 2. Distributed I-IP for ET&R

Built-in memory self-test Defect Analysis Redundancy allocation Repair Reconfiguration data download Retest

Composite IP for Embedded Memories

• 2. Quality & Reliability: Design
• 2. Quality & Reliability: Design

Highest defect coverage

Very deep submicron impact on defectivity in

embedded memories

Highest repair efficiency

Complex redundancy mechanisms Fault Detection and Localization Algorithms Reconfiguration Mechanisms Redundancy Allocation Algorithms Repair Methodology

• 2. Time
• 2. Time-
• to

to-

• Market: Design

Market: Design

Pre-Integrated F-IP and I-IP into a single SIP autonomous entity Interoperability: use of standard interface to I-IP, such as P1500

16

D

• Detection

A

• Analysis

C

• Correction

Characterization Characterization Characterization

Production Ramp Up Production Production Ramp Up Ramp Up

Volume Fabrication Volume Volume Fabrication Fabrication Test Assembly Packaging Test Test Assembly Assembly Packaging Packaging

In-Field In In-

• Field

Field

IP Design IP Design IP Design Failure Analysis Failure Failure Analysis Analysis SoC Design SoC Design SoC Design

• 3. Embedded Diagnosis IP
• 3. Embedded Diagnosis IP

C

A

D

5

• 3. Embedded Diagnosis IP
• 3. Embedded Diagnosis IP

Need to gather failure data using diagnosis IP and analyze obtained data by off-chip fault localization methodologies, tools and equipment Leverage same infrastructure IP for test, silicon debug and diagnosis Integrated Silicon Debug Solution comprised of -

Analysis & generate embedded test & diagnosis IP Integration & simulation of embedded test &

diagnosis IP

Creation of embedded test database Failure data from diagnosis IP analyzed off-chip for

fault localization

• 3. Infrastructure IP for Logic BIST
• 3. Infrastructure IP for Logic BIST

PRPG PRPG MISR MISR

scan chain scan chain scan chain scan chain scan chain logicBIST control & timing

Pseudo-Random Pattern Generator All flops placed into large number of relatively short scan chains Multiple Input Signature Register compresses responses into a signature Control unit sequences all activity

Source LogicVision

• 3. Logic BIST Test Sequence
• 3. Logic BIST Test Sequence

PRPG PRPG MISR MISR

scan chain scan chain scan chain scan chain scan chain logicBIST control & timing

PRPG SEED 1 PRPG SEED 1 MISR SEED 1 MISR SEED 1 1 1

SIG 10,000 SIG 10,000

3 2

10,000 loads, applications & unloads

Source LogicVision

• 3. Logic BIST Diagnosis
• 3. Logic BIST Diagnosis-
• Binary Search

Binary Search

P SEED 1 P SEED 1

SIG 5,000 SIG 5,000

M SEED 1 M SEED 1

PRPG PRPG MISR MISR

Logic BIST

5,000 loads, applications & unloads

P SEED 6,573 P SEED 6,573

SIG 6,573 SIG 6,573

M SEED 6,573 M SEED 6,573

PRPG PRPG MISR MISR

Logic BIST

1 load, application & unload

P SEED 5,001 P SEED 5,001

SIG 7,500 SIG 7,500

M SEED 5,001 M SEED 5,001

PRPG PRPG MISR MISR

Logic BIST

2,500 loads, applications & unloads Source LogicVision

• 3. Logic BIST Diagnosis
• 3. Logic BIST Diagnosis–

– Binary Search Binary Search

logicBIST control & timing

PRPG PRPG MISR MISR

Chain dump Chain dump

P SEED 6,573 P SEED 6,573

1 load, application, reconfiguration & scan out

Failing flops

Source LogicVision

Raw Datalog WGL

TRANSLATE

Tester Format

TRANSLATE

Design Data

T R A N S L A T E

VCD DFT

Design Engineer

Debug Cycle

Binary

COMPILE L O A D

• 3. Conventional Diagnosis Flow

• 3. Integrated Diagnosis Solution
• 3. Integrated Diagnosis Solution

Design Engineer eTest Database eTest Server Logic BIST Design Tool Test Engineer eTest TestStation

Source LogicVision

D

• Detection

A

• Analysis

C

• Correction

Characterization Characterization Characterization

Production Ramp Up Production Production Ramp Up Ramp Up

Volume Fabrication Volume Volume Fabrication Fabrication Test Assembly Packaging Test Test Assembly Assembly Packaging Packaging

In-Field In In-

• Field

Field

IP Design IP Design IP Design Failure Analysis Failure Failure Analysis Analysis SoC Design SoC Design SoC Design

• 4. Embedded Timing IP
• 4. Embedded Timing IP

D A

C

4

• 4. Embedded Timing IP
• 4. Embedded Timing IP
• 4. Embedded Timing IP

Very stringent timing specification Difficulty in obtaining accurate measurements using external instrumentation Embedded timing IP [Tabatabaei 02] comprised of

Multiple high speed probes Embedded control core directs probes and transfers

information to timing processor for analysis

Yield gain obtained due to accurate measurement

• 4. Yield Gain due to Timing IP
• 4. Yield Gain due to Timing IP

Accepted per DAC Increased Tolerance

Yield Improvement

Timing Specification Chip Spec GOOD CHIP BAD CHIP Not accepted Accepted

Source: Vector 12

D

• Detection

A

• Analysis

C

• Correction

Characterization Characterization Characterization

Production Ramp Up Production Production Ramp Up Ramp Up

Volume Fabrication Volume Volume Fabrication Fabrication Test Assembly Packaging Test Test Assembly Assembly Packaging Packaging

In-Field In In-

• Field

Field

IP Design IP Design IP Design Failure Analysis Failure Failure Analysis Analysis SoC Design SoC Design SoC Design

• 5. Embedded Robustness IP
• 5. Embedded Robustness IP

D A

C

7

• 5. Field Reliability Challenge
• 5. Field Reliability Challenge

100000 1000 100 0.1 10 1 10000 0.05 0.1 0.15 0.2 0.25

1997 1999 2001 2003 2005 2008 2012

N

• r

m l i z e d F I T R a t e From AMD, Intel, Compaq, 1999

The error bars account for the range

• f supply voltage.

The SER increases exponentially at 2.1-2.2 decades/volt, e.g 200X in 2005.

• 5. Soft
• 5. Soft Error Risk

Error Risk

2 4 6 8 10 12 14 16 18 20

0.25 0.18 0.13

a.u

Voltage Area Speed Perfmnce = V*S*A

A 0.13µm design offers 40X more performance than 0.25µm … but is 40X more prone to Soft Errors

• 5. Robustness IP for ECC
• 5. Robustness IP for ECC
• Standard ECC architecture provides

single bit repair and adds extra delay to each read and write operation

Memory IP Memory Memory IP IP ECC generator ECC ECC generator generator Syndrome Generator Syndrome Syndrome Generator Generator Error Logic Error Error Logic Logic

Correction Block Correction Correction Block Block

code code bits bits Data Bus Data Bus Error Error Indication Indication

code code bits bits

Data Bus Data Bus

• 5. Robustness IP for Random Logic
• 5. Robustness IP for Random Logic

f f

n m

Protected Function Data Predictor Data Predictor Checker Checker Error Signal

Robustness Block

Original IC

Source: iRoC Technologies

Conclusions Conclusions Conclusions

Leveraging I-IP for higher yield and reliability Leveraging I-IP for Time-to-Volume Acceleration Infrastructure IP may require external support, automated tools and equipment Yield optimization loops leveraged at different product realization steps during design, fabrication, test and in-field Collaborative Environment is necessary to achieve Yield, Quality and TTV goals