Embedded Quality for Test Embedded Quality for Test Yervant Zorian - - PowerPoint PPT Presentation

Embedded Quality for Test Embedded Quality for Test

Yervant Zorian Yervant Zorian LogicVision, Inc. LogicVision, Inc.

Electronics I ndustry Electronics I ndustry

I I Achieved Successful

Achieved Successful Penetration Penetration in Diverse in Diverse Domains Domains

Electronics I ndustry ( Electronics I ndustry ( cont cont) )

I I Met User

Met User Quality Quality Requirements Requirements

– – satisfying users’ to buy products satisfying users’ to buy products again again Created an Unprecedented Dependency

• market-driven product

Electronic Product

Competitors U s e r s

Quality Requirements at Chip Level Quality Requirements at Chip Level

I I Manufacturing Test for Chips

Manufacturing Test for Chips

I To achieve board defect levels < 1%

To achieve board defect levels < 1%

I To maintain ATE cost

To maintain ATE cost

I I Diagnostics for Chip Manufacturing

Diagnostics for Chip Manufacturing

I To enable physical failure analysis

To enable physical failure analysis

I To enhance yield by enabling repair for large memories

To enhance yield by enabling repair for large memories

Quality Requirements at Board Level Quality Requirements at Board Level

I I Board Level Manufacturing Test

Board Level Manufacturing Test

I Full Coverage of board level defects

Full Coverage of board level defects

I Chip failures (handling, stress, infant mortality)

Chip failures (handling, stress, infant mortality)

I I Diagnostics for Board Level Manufacturing

Diagnostics for Board Level Manufacturing

I To determine failed interconnect or chip

To determine failed interconnect or chip

I To enable speedy repair

To enable speedy repair

Conventional Test Flow Conventional Test Flow

I I Functional Patterns

Functional Patterns

I I Deterministic ATPG

Deterministic ATPG with Scan Path with Scan Path

I I Full Pin Count

Full Pin Count Automatic Test Automatic Test Equipment Equipment

Emerging Electronics I ndustry Emerging Electronics I ndustry

I I Products Shift to Communications and Connectivity

Products Shift to Communications and Connectivity

I I Maintain competitive edge by providing:

Maintain competitive edge by providing:

– – Greater Product Greater Product Functionality Functionality – – Lower Lower Cost Cost (product life cycle) (product life cycle) – – Reduced Reduced Time-to-Profitability Time-to-Profitability – – Higher Quality and Higher Quality and Reliability Reliability

Emerging I nfrastructure Emerging I nfrastructure

“The internet runs on silicon.” “The internet runs on silicon.”

Andy Grove

Andy Grove

“The information superhighway “The information superhighway is paved in silicon.” is paved in silicon.”

Scott McNealey Scott McNealey

Emerging I ndustry Trends Emerging I ndustry Trends

I I Caused new technologies:

Caused new technologies:

Greater Greater Complexity Complexity Increased Increased Performance Performance Higher Higher Density Density Lower Lower Power Power Dissipation Dissipation

The Key Challenge The Key Challenge

I I To meet Users’ Quality Requirements for

To meet Users’ Quality Requirements for new Technologies new Technologies

I I To assure New Products are adequately:

To assure New Products are adequately: Tested, Verified, Measured, Debugged, Repaired, ...

Emerging New Challenges Emerging New Challenges

I I Observe Implications on Product Realization

Observe Implications on Product Realization

I I Analyze Existing Quality Assurance Approaches

Analyze Existing Quality Assurance Approaches

I I Identify Challenges

Identify Challenges

I I Demonstrate Potential Solutions

Demonstrate Potential Solutions

Design Manufacturing

• Diag. & Yield

Field Service

Design Challenge: Quality Design Challenge: Quality

I I Implication:

Implication:

– – # of Transistors per pin # of Transistors per pin (Testing Complexity (Testing Complexity Index) Index)

Testing Complexity Index - [#Tr. per Pin]

1992 0.5 2007 2004 2001 1998 1995 1.60E+ 5 0.1 0.12 018 0.25 0.35 1.00E+ 5 1.40E+ 5 4.00E+ 4 2.00E+ 4 0.00E+ 0 6.00E+ 4 8.00E+ 5

Implications of SIA Roadmap: Testing

• F. Size [µm]

Year

Source: W. Maly, 1996

Source: SIA Roadmap

– increased internal speed increased internal speed vs vs external external

Design Manufacturing

• Diag. & Yield

Field Service

Design Challenge: Quality Design Challenge: Quality

I I Leverage Internal Bandwidth

Leverage Internal Bandwidth vs vs External External Bandwidth Bandwidth

ASIC DRAM

I/O Drivers I/O Drivers

• ff-chip bus

32-bits

ASIC DRAM

• n-chip bus

128/512-bits

System-on-Chip

Design Challenge: Quality Design Challenge: Quality

I I External Bandwidth

External Bandwidth

– – max bits of data/time max bits of data/time from ATE to IC from ATE to IC

I I Bandwidth Gap

Bandwidth Gap

I I Internal Bandwidth

Internal Bandwidth

max bits of data/time from on- max bits of data/time from on- chip test resource to chip test resource to embedded core embedded core

Internal Bdw.

(Capacity*IntFreq

External Bdw

(IO*ExtFreq)

50 100 150 200 250

Y 1 9 9 5 Y1998 Y 2 1 Y 2 4 Y2007 Y2010

Bandwidth Gap

Design Challenge: Quality Design Challenge: Quality

I I External Test Data Volume

External Test Data Volume can be extremely high can be extremely high (function of chip (function of chip complexity) complexity)

I I Requires deep tester

Requires deep tester memory for scan I/O pins memory for scan I/O pins

I I Slow test throughput with

Slow test throughput with long scan chains, especially long scan chains, especially for core-based designs for core-based designs

External Test

Super Tester Pattern Generation Precision Timing Diagnostics Power Management Test Control Very high pin count Deep memory

Slow throughput Logic

.

Mixed- Signal Memory I/Os &

Interconnects

Design Challenge: Quality Design Challenge: Quality

I I Solution: Dedicated Built-In

Solution: Dedicated Built-In H/W for embedded test H/W for embedded test functions functions

External Test

Standard Digital Tester Limited Speed/ Accuracy Low Cost-per-Pin

Embedded Test

(Built-in) Pattern Generation Result Compression Precision Timing Diagnostics Power Management Test Control Support for Board-level Test System-Level Test

Logic

.

Mixed- Signal Memory I/Os &

Interconnects

Chip, Board or System

Source: LogicVision

I I Repartition tester into

Repartition tester into embedded test and embedded test and external test functions external test functions

I I Include low H/W cost

Include low H/W cost and high data volume and high data volume embedded-quality for test embedded-quality for test

Source/ Sink

Test Access

External Test

Source/ Sink

External Test Embedded Test

Scan Paths

Source/ Sink

High- Bandwidth

External Test Embedded Test

Source/ Sink

High bandwidth

Low - bandwidth

Source/ Sink

External Test Embedded Test

Design Challenge: Quality

Design Challenge: Quality

Design Challenge: TTM Design Challenge: TTM

I I Multiple hardware

Multiple hardware description levels description levels (hard, soft, firm) (hard, soft, firm)

I I Standard IC functions

Standard IC functions (library elements) and (library elements) and legacy cores legacy cores

Source: VSI Alliance

I I Implication: Emergence

Implication: Emergence

• f reusable core-based
• f reusable core-based

design design

1998 1999 2000 2001 2002 2003

Worldwide Revenue (Billions of Dollars)

SOC Market Growth SOC Market Growth

30 25 20 15 10 5 Source: Dataquest

Paradigm Shift in SOC Design Paradigm Shift in SOC Design

System on a board System on a Chip

Design Challenge: TTM Design Challenge: TTM

I I SOC manufactured and

SOC manufactured and tested in single stage tested in single stage

I I Core I/Os often more than

Core I/Os often more than Chip I/Os Chip I/Os

I I Test generation difficult due

Test generation difficult due to limited core design to limited core design knowledge knowledge

I I Direct access to core ports

Direct access to core ports unavailable unavailable

I I Core & UDL test part of

Core & UDL test part of System-On-Chip test System-On-Chip test

System-on-Board (SOB) Process System-on-Chip (SOC) Process

IC Design IC Manuf. ASIC Manuf. ASIC Design SOB Manuf. SOB Test Core Design SOB Design UDL Design SOC Integration IC Test ASIC Test SOC Manuf. SOC Test

Design Challenge: TTM Design Challenge: TTM

I I Built-in dedicated H/W to

Built-in dedicated H/W to create create autonomous autonomous internal core test internal core test

I I Built-in dedicate System-

Built-in dedicate System- On-Chip On-Chip test optimization test optimization

I Built-In

Built-In standard standard core test core test interface for each core interface for each core

Design Challenge: TTM Design Challenge: TTM

I I IEEE P1500 (9/96) develops a

IEEE P1500 (9/96) develops a standard for standard for embedded core test interface embedded core test interface comprised of: comprised of:

– – Standard Core Test Information Model (CTL) using a Standard Core Test Information Model (CTL) using a Standard Description Language (STIL) Standard Description Language (STIL) – – Standard Core Test Wrapper and Control Mechanism Standard Core Test Wrapper and Control Mechanism – – Phase 1: Phase 1: Dual Dual Compliance for Digital Cores (1149.1) Compliance for Digital Cores (1149.1) – – Phase 2: Analog Cores (1149.4), Testability Guidelines Phase 2: Analog Cores (1149.4), Testability Guidelines

I I VSI Manufacturing Test Related DWG

VSI Manufacturing Test Related DWG supports IEEE P1500 standardization supports IEEE P1500 standardization

Design Challenge: TTM Design Challenge: TTM

Boundary Scan Chain Boundary Scan Chain 1149.1 TAP TDI TDO TCK TMS TRST

Logic BIST

Glue Logic

BIST Enabled Core

TP

Logic BIST

BIST Enabled Core

TP

Logic BIST

BIST Enabled Core

TP

Logic BIST

BIST Enabled Core

TP

Logic BIST

Glue Logic

Memory BIST

Design Challenge: Quality Design Challenge: Quality

I I Implication: Increased chip internal speed

Implication: Increased chip internal speed

( (ASSP with 200MHz+ , Microprocessors with 1

ASSP with 200MHz+ , Microprocessors with 1 GHz GHz+ ) + ) – – Multiple and overlapping clock domains Multiple and overlapping clock domains – – Multi-cycle data paths Multi-cycle data paths – – Complex clock distribution Complex clock distribution

I I Recent SEMATECH study revealed criticality of

Recent SEMATECH study revealed criticality of performance faults performance faults

Design Challenge: Quality Design Challenge: Quality

I I High speed ATE substantially

High speed ATE substantially more expensive more expensive

I I ATE

ATE vs vs Chip Technology Chip Technology discrepancy: Tester uses 5 year discrepancy: Tester uses 5 year

• ld technology - chips move to
• ld technology - chips move to

next generation every 2 years next generation every 2 years

I I ATE accuracy degrading: Chip

ATE accuracy degrading: Chip cycle time will crossover ATE cycle time will crossover ATE accuracy accuracy

1 1 10 10 100 100 1000 1000

1980 1980 1985 1985 1990 1990 1995 1995 2000 2000 2005 2005 2010 2010 2015 2015

Time in Time in nS nS, Yield loss in % , Yield loss in %

ATE OTA( ATE OTA(nS nS) ) device speed (nS)

projected yield loss (%) projected yield loss (%)

Design Challenge: Quality Design Challenge: Quality

I I Solution: Built-In dedicated

Solution: Built-In dedicated H/W to run Built-In Self-Test H/W to run Built-In Self-Test at-speed and detect at-speed and detect performance faults performance faults

Source: Sun Microsystems

I I Major move for mainstream

Major move for mainstream systems to implement at-speed systems to implement at-speed BIST for production test BIST for production test

Manufacturing Challenge: Test Cost Manufacturing Challenge: Test Cost

I I Embed in a single chip:

Embed in a single chip: Logic, Analog, DRAM blocks Logic, Analog, DRAM blocks

I I Embed advanced

Embed advanced technology blocks: technology blocks:

– – FPGA, Flash, RF/Microwave FPGA, Flash, RF/Microwave

I I Beyond Electronic blocks:

Beyond Electronic blocks:

– – MEMS MEMS – – Optical elements Optical elements

µP

Memory

Memory Memory

Core

Logic

Logic

Logic

Logic

Mixed Signal

Design Manufacturing

• Diag. & Yield

Field Service

Manufacturing Challenge: Test Cost Manufacturing Challenge: Test Cost Multiple Insertions or Super ATE!

W(5FB 8A3) R(4C2 9E0) …

Functional Tester

W(5FB 8A3) R(4C2 9E0) …

Logic Tester

W(5FB 8A3) R(4C2 9E0) …

Memory Tester

W(5FB 8A3) R(4C2 9E0) …

Mixed-Signal Tester

µP

Memory

Memory Memory

Core

Logic

Logic

Logic

Logic

Mixed Signal

Moore’s Moore’s Law for Test Law for Test

Cost of Silicon Cost of Silicon Mfg Mfg and Test and Test

0.0000001 0.0000001 0.000001 0.000001 0.00001 0.00001 0.0001 0.0001 0.001 0.001 0.01 0.01 0.1 0.1 1 1 1982 1982 1985 1985 1988 1988 1991 1991 1994 1994 1997 1997 2000 2000 2003 2003 2006 2006 2009 2009 2012 2012

cost: cents /transistor cost: cents /transistor

Si Si capital / transistor capital / transistor Test capital / transistor Test capital / transistor

Based on SIA Roadmap Data Based on SIA Roadmap Data

Manufacturing Challenge: Test Cost Manufacturing Challenge: Test Cost

LogicVision’s Embedded Test

µP

Memory

Memory Memory

Logic

Logic

Logic

Mixed Signal

Logic

Core

Low Cost Sort Machine with LogicVision BIST Access Software

I/O’s tri-stated no critical timing

If full scan already exists then the dues are already paid JTAG 4 Pin Interface

Manufacturing Challenge: Quality Manufacturing Challenge: Quality

I I High Density Chips: Advanced Semiconductor

High Density Chips: Advanced Semiconductor Technology with very high density Technology with very high density

I I number of millions of transistors per sq. cm.

number of millions of transistors per sq. cm. will increase by a factor of three in next five will increase by a factor of three in next five years years

I I Test Escape due to

Test Escape due to unmodeled unmodeled faults (ex: SOI faults (ex: SOI process, Copper Interconnect) process, Copper Interconnect)

– – Use built-In dedicated h/w to execute fault Use built-In dedicated h/w to execute fault model independent pseudo-random model independent pseudo-random pattern based test pattern based test

Manufacturing Challenge: Quality Manufacturing Challenge: Quality

I I Challenge: High

Challenge: High performance board and performance board and MCM applications (ex: MCM applications (ex: 500MHz chip-to-chip) 500MHz chip-to-chip)

I I Require Chip-to-Chip

Require Chip-to-Chip Interconnect test for Interconnect test for static and dynamic static and dynamic faults faults

Source: Stratus Computers

Source: Stratus Computers

Manufacturing Challenge: Quality Manufacturing Challenge: Quality

I I Solution:

Solution:

– – IEEE 1149.1 Boundary- IEEE 1149.1 Boundary- Scan for static faults Scan for static faults – – At-Speed Interconnect At-Speed Interconnect Test requires Built-In Test requires Built-In dedicated H/W dedicated H/W

Diagnosis & Yield Challenge: Cost Diagnosis & Yield Challenge: Cost

I I Implication: Large Embedded:

Implication: Large Embedded: SRAM, DRAM, Flash SRAM, DRAM, Flash

I I Beyond certain size memories

Beyond certain size memories necessitate redundancy/repair necessitate redundancy/repair during manufacturing test during manufacturing test (and field reliability) (and field reliability)

I I Requires Logic ATE, Memory

Requires Logic ATE, Memory ATE, Laser Repair Equipment, ATE, Laser Repair Equipment, and Redundancy Analysis and Redundancy Analysis

Design Manufacturing

• Diag. & Yield

Field Service

Diagnosis & Yield Challenge: Cost Diagnosis & Yield Challenge: Cost

I I Two reconfiguration strategies:

Two reconfiguration strategies:

• 1. Hard: Built-in dedicated h/w for
• 1. Hard: Built-in dedicated h/w for

Redundancy Analysis and Redundancy Analysis and external repair (fuse blow) external repair (fuse blow)

• 2. Soft: Built-In dedicated
• 2. Soft: Built-In dedicated

reconfiguration mechanism reconfiguration mechanism using BISR (test repeatability) using BISR (test repeatability)

I I Adopted by several chip

Adopted by several chip manufacturers manufacturers

Memory test Analysis & Reconf Logic test (wafer) Packaging Logic test (package) Memory retest WAFER

Memory Repair

Pass/Fail

Testing/Repair of ASIC with Large Embedded Memory

Diagnosis & Yield Challenge: TTM Diagnosis & Yield Challenge: TTM

I I Advanced Packaging Technologies

Advanced Packaging Technologies

– – Increased use of Flip-Chip Technology: Flip-Chip design Increased use of Flip-Chip Technology: Flip-Chip design dedicates a dedicates a metal layer metal layer for area array interconnects for area array interconnects (Direct Chip Attach, Chip Scale Packaging, BGA and MCM) (Direct Chip Attach, Chip Scale Packaging, BGA and MCM) – – Increased use of Fine-Pitch Technology: probing Increased use of Fine-Pitch Technology: probing limitations due to miniaturized package technologies (FC, limitations due to miniaturized package technologies (FC, CSP) -> very expensive probe cards CSP) -> very expensive probe cards – – Increased use of bare die usage -> inadequacy of Increased use of bare die usage -> inadequacy of conventional package test (Direct Chip Attach, MCM) conventional package test (Direct Chip Attach, MCM)

Diagnosis & Yield Challenge: TTM Diagnosis & Yield Challenge: TTM

I I Conventional failure mode

Conventional failure mode analysis based on E-beam can analysis based on E-beam can not be used with flip-chip not be used with flip-chip

I I Solution: Use Embedded

Solution: Use Embedded Quality functions for Quality functions for diagnosis: stop-on-error, data diagnosis: stop-on-error, data logging for memories, and logging for memories, and scan-based diagnosis for scan-based diagnosis for random logic. This can be random logic. This can be leveraged for interactive at- leveraged for interactive at- speed diagnosis. speed diagnosis.

Flip-chip die

Diagnosis & Yield Challenge: TTM Diagnosis & Yield Challenge: TTM

I I Conventional failure mode

Conventional failure mode analysis based on E-beam can analysis based on E-beam can not be used with flip-chip not be used with flip-chip

I I Solution: Use Embedded

Solution: Use Embedded Quality functions for Quality functions for diagnosis: stop-on-error, data diagnosis: stop-on-error, data logging for memories, and logging for memories, and scan-based diagnosis for scan-based diagnosis for random logic. This can be random logic. This can be leveraged for interactive at- leveraged for interactive at- speed diagnosis. speed diagnosis.

Flip-chip die

Diagnosis & Yield Challenge: TTM Diagnosis & Yield Challenge: TTM

– –Source HPL, Inc. Source HPL, Inc.

Diagnosis & Yield Challenge: TTM Diagnosis & Yield Challenge: TTM

– –Source HPL, Inc. Source HPL, Inc.

Field Challenge: Quality Field Challenge: Quality

I I Challenge: Increase Impact of Cosmic

Challenge: Increase Impact of Cosmic Radiation on Sea Level Radiation on Sea Level

I I Solutions: Embedded test dedicated

Solutions: Embedded test dedicated h/w function for On-line BIST to detect h/w function for On-line BIST to detect transient (soft) errors transient (soft) errors

Design Manufacturing

• Diag. & Yield

Field Service

Field Challenge: Cost, TTM Field Challenge: Cost, TTM

I I Design and Manufacturing of Complex Boards and

Design and Manufacturing of Complex Boards and Systems costs too much and takes too long Systems costs too much and takes too long

I I Test development cost

Test development cost is 35% of total product is 35% of total product development time development time

I I Test, Diagnosis and Repair cost

Test, Diagnosis and Repair cost for complex systems for complex systems reaches 40-50% of total product realization cost reaches 40-50% of total product realization cost

ATE / Hardware Interface (accessible by connector) for Manufacturing or Field OS / Software Interface (accessible by network) at the Application layer Box Hardware Software Operating System and Applications

Source: LogicVision Reuse of dedicated built-in quality hardware

EQ Board EQ SOC Service Kernel EQ

Hierarchical Embedded Test Hierarchical Embedded Test

Test Cost as % of Total Life Cycle Cost 5 10 15 20 25 30 3 10 16.4

Without

Built-In Quality 29.4 %

Source: AeroSpace Study

Field Challenge: Cost, TTM Field Challenge: Cost, TTM

I I Leveraging dedicated

Leveraging dedicated Embedded Quality Embedded Quality function drastically function drastically reduces test reduces test development interval development interval and test costs and test costs

With

Built-In Quality 3.6 2.5 1.6 7.7 %

Conventional Quality Paradox Conventional Quality Paradox

Design Test Management “It is really not my problem, but I will do what I can to help out.” Manufacturing Test Management “I have little control on the design process! I will buy the best testers possible and perform as much testing as possible to ensure the expected quality.”

A Solution that Combines the Best of DFT and ATE

Embedded Test H/W Automation Tools Test Programs Diagnostic Data

Test Test Resource Partitioning

Resource Partitioning

Logic Tester Memory Tester Mixed Signal Tester Processor Tester Board Tester External ATE Scan Design Isolation & Access Random Pattern BIST Algorithmic BIST 1149.1 TAP/BSCAN DFT Methods

Conclusions Conclusions

I I To ensure quality of electronic products using emerging

To ensure quality of electronic products using emerging technologies: technologies: – – Embedded Quality functions are added into the high level Embedded Quality functions are added into the high level designs of embedded cores, designs of embedded cores, SOCs SOCs, board and systems , board and systems

I I A range of Embedded Quality functions provide adequate

A range of Embedded Quality functions provide adequate test, verification, diagnosis, debug, measurement and repair test, verification, diagnosis, debug, measurement and repair

Design Manufacturing

• Diag. & Yield

Field Service

Thank YOU Thank YOU for your attention for your attention