System-on-Chip Design HW/SW Interfaces and Communica;ons Hao Zheng - PowerPoint PPT Presentation

System-on-Chip Design HW/SW Interfaces and Communica;ons Hao Zheng Comp Sci & Eng U of South Florida 1

System Structural Model Mem CPU P1 P2 Arbiter Bridge P3 P5 P4 HW HW 2

Basic Elements of HW/SW Interfaces 1. On-chip communicaCon fabrics, ex. buses 3

Basic Elements of HW/SW Interfaces 2. CPU interface for SW to communicate with custom HW. 4

Basic Elements of HW/SW Interfaces 3. HW interface for custom HW to communicate with CPU. 5

Basic Elements of HW/SW Interfaces 4. SW driver converts SW IO operaCons to operaCons supported by CPU interface. 6

Basic Elements of HW/SW Interfaces 5. Programming model where SW running CPU uses to control custom HW module. 7

Synchroniza;on Schemes SynchronizaCon is necessary for effecCve communicaCons, i.e. data transferred between CPU and HW correctly. SynchronizaCon is part of interface implementaCon. 8

Synchroniza;on Schemes Time : how synchronizaCon is defined over Cme. 9

Synchroniza;on Schemes Data : how data is represented in synchronizaCon. 10

Synchroniza;on Schemes Control : how synchronizaCon is implemented locally in individual modules.. 11

Semaphores • Used to control of accesses to shared resource. • Two ops on semaphore S : – P(S): acquire S . thread 2: thread 1: – V(S): release S . … … • How can we ensure an P(S); P(S); order between thread x = x – 2; x++; 1 & 2? V(s); V(s); … … 12

enCty two { enCty one { Semaphores short_delay(); P(S); while (1) { while (1) { P(S); short_delay(); int shared_data; rd = shared_data; shared_data = …; semaphore S; }} V(S); }} 13

Semaphores • Semaphores can only guarantee exclusive access to shared resources. – Difficult to control precise data transfer – MulCple semaphores can be used, but not elegant. • Handshaking : a signaling protocol between two enCCes to coordinate data transfers. – Can handle enCCes with different speeds. 14

One-Way Handshake Assume that enCty two is slower. 15

Two-Way Handshake 16

Two-Way Handshake for Data Transfer req ack Dest Src data clk req ack X X X X X X X X X data d1 17

Communica;on Constrained vs Computa;on Constrained System performance should consider both computaCon performance and communicaCon overhead. 18

Communica;on Constrained vs Computa;on Constrained 19

Tight and Loose Coupling Coupling : the level of interacCons between two components. Degree of coupling affects choice and implementaCon of synchronizaCon. 20

Dedicated vs Shared Interfaces Nature of coupling affects the organizaCon of HW/SW interfaces Coprocessor Memory-mapped Factor interface interface Addressing Processor-specific On-chip bus address Connection Point-to-point Shared Latency Fixed Variable Throughput Higher Lower Cght loose coupling coupling 21

Reading Guide • Chapter 9, the CoDesign book. 22