stvec a vector instruction extension for high performance
play

StVEC: A Vector Instruction Extension for High Performance Stencil - PowerPoint PPT Presentation

Mar 21, 2024 •132 likes •733 views

StVEC: A Vector Instruction Extension for High Performance Stencil Computation Renji Thomas Louis-No el Pouchet Naser Sedaghati Radu Teodorescu P. Sadayappan Department of Computer Science and Engineering The Ohio State University HPC

  1. StVEC: A Vector Instruction Extension for High Performance Stencil Computation Renji Thomas Louis-No¨ el Pouchet Naser Sedaghati Radu Teodorescu P. Sadayappan Department of Computer Science and Engineering The Ohio State University HPC Research Lab: barista.cse.ohio-state.edu Computer Architecture Lab: arch.cse.ohio-state.edu October 13 th 2011 Naser Sedaghati (CSE @ Ohio State) StVEC: A Vector Instruction Extension PACT’11 1 / 24

  2. Outline Introduction 1 Vectorization of Stencils 2 Enhancing Vector ISA with StVEC 3 Generating Code for StVEC 4 Evaluation 5 Summary 6 Naser Sedaghati (CSE @ Ohio State) StVEC: A Vector Instruction Extension PACT’11 2 / 24

  3. Introduction Stencil Computation Repeat over TIME Sweep over a spatial grid Compute a point from neighbor points values Same grid or multiple grids Numerous application domains Finite difference methods for solving PDEs Image processing (e.g. MRI image pipeline) Computational electromagnetics, CFD, numerical relativity, etc. Naser Sedaghati (CSE @ Ohio State) StVEC: A Vector Instruction Extension PACT’11 3 / 24

  4. Introduction Stencil Computation: An Example 2-D 5-point Jacobi for (t = 0; t < TMAX; t++) for (i = 1; i < N - 1; i++) for (j = 1; j < M - 1; j++) B[i][j] = A[i-1][j] + A[i][j-1] + A[i ][j] + A[i][j+1] + A[i+1][j]; Naser Sedaghati (CSE @ Ohio State) StVEC: A Vector Instruction Extension PACT’11 4 / 24

  5. Introduction Stencil Computation: An Example 2-D 5-point Jacobi for (t = 0; t < TMAX; t++) for (i = 1; i < N - 1; i++) for (j = 1; j < M - 1; j++) B[i][j] = A[i-1][j] + A[i][j-1] + A[i ][j] + A[i][j+1] + A[i+1][j]; Naser Sedaghati (CSE @ Ohio State) StVEC: A Vector Instruction Extension PACT’11 4 / 24

  6. Introduction Stencil Computation: An Example 2-D 5-point Jacobi for (t = 0; t < TMAX; t++) for (i = 1; i < N - 1; i++) for (j = 1; j < M - 1; j++) B[i][j] = A[i-1][j] + A[i][j-1] + A[i ][j] + A[i][j+1] + A[i+1][j]; Naser Sedaghati (CSE @ Ohio State) StVEC: A Vector Instruction Extension PACT’11 4 / 24

  7. Introduction Stencil Computation: An Example 2-D 5-point Jacobi for (t = 0; t < TMAX; t++) for (i = 1; i < N - 1; i++) for (j = 1; j < M - 1; j++) B[i][j] = A[i-1][j] + A[i][j-1] + A[i ][j] + A[i][j+1] + A[i+1][j]; Naser Sedaghati (CSE @ Ohio State) StVEC: A Vector Instruction Extension PACT’11 4 / 24

  8. Introduction Short-Vector SIMD Identical computation on small chunks of data Independent operations Vector size (width) of 2 to 64 Packing operations to form a vector (shuffle, extract, etc.) SIMD performance Multiple SIMD units per CPU Maximum speedup equals the vector width Ubiquitous features on modern processors x86 – SSE, AVX Power – VMX/VSX ARM – NEON Cell SPU Naser Sedaghati (CSE @ Ohio State) StVEC: A Vector Instruction Extension PACT’11 5 / 24

  9. Introduction Vectorization: An Example Vector width = 4, N divisible by 4 for (t = 0; t < T; t++) for (i = 4; i < N; i++) A[i] = B[i] * B[i] ; Naser Sedaghati (CSE @ Ohio State) StVEC: A Vector Instruction Extension PACT’11 6 / 24

  10. Introduction Vectorization: An Example Vector width = 4, N divisible by 4 for (t = 0; t < T; t++) for (i = 4; i < N; i++) A[i] = B[i] * B[i] ; 1: ASM (MIPS-like) for (t = 0; t < T; t++) for (i = 4; i < N; i++){ LD R1, &B[i] MUL R2, R1, R1 ST R2, &A[i] } Naser Sedaghati (CSE @ Ohio State) StVEC: A Vector Instruction Extension PACT’11 6 / 24

  11. Introduction Vectorization: An Example Vector width = 4, N divisible by 4 for (t = 0; t < T; t++) for (i = 4; i < N; i++) A[i] = B[i] * B[i] ; 1: ASM (MIPS-like) 2: 4-way unroll + re-schedule for (t = 0; t < T; t++) for (t = 0; t < T; t++) for (i = 4; i < N; i++){ for (i = 4; i < N; i+=4){ LD R1, &B[i] LD R1, &B[i] MUL R2, R1, R1 LD R2, &B[i+1] LD R3, &B[i+2] ST R2, &A[i] LD R4, &B[i+3] } MUL R5, R1, R1 MUL R6, R2, R2 MUL R7, R3, R3 MUL R8, R4, R4 ST R5, &A[i] ST R6, &A[i+1] ST R7, &A[i+2] ST R8, &A[i+3] } Naser Sedaghati (CSE @ Ohio State) StVEC: A Vector Instruction Extension PACT’11 6 / 24

  12. Introduction Vectorization: An Example Vector width = 4, N divisible by 4 for (t = 0; t < T; t++) for (i = 4; i < N; i++) A[i] = B[i] * B[i] ; 1: ASM (MIPS-like) 2: 4-way unroll + re-schedule 3: Vectorize for (t = 0; t < T; t++) for (t = 0; t < T; t++) for (t = 0; t < T; t++) for (i = 4; i < N; i+=4){ for (i = 4; i < N; i++){ for (i = 4; i < N; i+=4){ VLD VR1, &B[i] LD R1, &B[i] LD R1, &B[i] VMUL VR2, VR1, VR1 MUL R2, R1, R1 LD R2, &B[i+1] VST VR2, &A[i] LD R3, &B[i+2] ST R2, &A[i] } LD R4, &B[i+3] } MUL R5, R1, R1 MUL R6, R2, R2 MUL R7, R3, R3 MUL R8, R4, R4 ST R5, &A[i] ST R6, &A[i+1] ST R7, &A[i+2] ST R8, &A[i+3] } Naser Sedaghati (CSE @ Ohio State) StVEC: A Vector Instruction Extension PACT’11 6 / 24

  13. Introduction Vectorization: An Example Vector width = 4, N divisible by 4 for (t = 0; t < T; t++) for (i = 4; i < N; i++) A[i] = B[i] * B[i] ; 1: ASM (MIPS-like) 2: 4-way unroll + re-schedule 3: Vectorize for (t = 0; t < T; t++) for (t = 0; t < T; t++) for (t = 0; t < T; t++) for (i = 4; i < N; i+=4){ for (i = 4; i < N; i++){ for (i = 4; i < N; i+=4){ VLD VR1, &B[i] LD R1, &B[i] LD R1, &B[i] VMUL VR2, VR1, VR1 MUL R2, R1, R1 LD R2, &B[i+1] VST VR2, &A[i] LD R3, &B[i+2] ST R2, &A[i] } LD R4, &B[i+3] } MUL R5, R1, R1 MUL R6, R2, R2 MUL R7, R3, R3 MUL R8, R4, R4 ST R5, &A[i] ST R6, &A[i+1] ST R7, &A[i+2] ST R8, &A[i+3] } Observation Aligned memory referencing (i.e. B[i]) helps vectorization! Naser Sedaghati (CSE @ Ohio State) StVEC: A Vector Instruction Extension PACT’11 6 / 24

  14. Vectorization of Stencils Vectorization of Stencils Naser Sedaghati (CSE @ Ohio State) StVEC: A Vector Instruction Extension PACT’11 7 / 24

  15. Vectorization of Stencils Vectorizing Stencil Computation for (t = 0; t < T; t++) for (i = 4; i < N; i++) A[i] += B[i-1] * B[i]; Naser Sedaghati (CSE @ Ohio State) StVEC: A Vector Instruction Extension PACT’11 8 / 24

  16. Vectorization of Stencils Vectorizing Stencil Computation for (t = 0; t < T; t++) for (i = 4; i < N; i++) A[i] += B[i-1] * B[i]; Solution1: load + shuffle B[ ] in XMM Registers SSE Assembly (N=1024) Naser Sedaghati (CSE @ Ohio State) StVEC: A Vector Instruction Extension PACT’11 8 / 24

  17. Vectorization of Stencils Vectorizing Stencil Computation for (t = 0; t < T; t++) for (i = 4; i < N; i++) A[i] += B[i-1] * B[i]; Solution1: load + shuffle Solution2: unaligned load B[ ] in XMM Registers SSE Assembly (N=1024) Naser Sedaghati (CSE @ Ohio State) StVEC: A Vector Instruction Extension PACT’11 8 / 24

  18. Vectorization of Stencils Vectorizing Stencil Computation for (t = 0; t < T; t++) for (i = 4; i < N; i++) A[i] += B[i-1] * B[i]; Solution1: load + shuffle Solution2: unaligned load Our Solution: StVEC (no shuffle, no unaligned load) B[ ] in XMM Registers SSE Assembly (N=1024) Naser Sedaghati (CSE @ Ohio State) StVEC: A Vector Instruction Extension PACT’11 8 / 24

  19. Enhancing Vector ISA with StVEC Enhancing Vector ISA with StVEC Naser Sedaghati (CSE @ Ohio State) StVEC: A Vector Instruction Extension PACT’11 9 / 24

  20. Enhancing Vector ISA with StVEC Execution Model Building Unaligned Vector Operands Idea: build an unaligned operand during register read Only one unaligned operand suffice for stencils Naser Sedaghati (CSE @ Ohio State) StVEC: A Vector Instruction Extension PACT’11 10 / 24

  21. Enhancing Vector ISA with StVEC Execution Model Building Unaligned Vector Operands Idea: build an unaligned operand during register read Only one unaligned operand suffice for stencils Build the unaligned operand (i.e. VOPR x ) with two source regs base and extension Naser Sedaghati (CSE @ Ohio State) StVEC: A Vector Instruction Extension PACT’11 10 / 24

  22. Enhancing Vector ISA with StVEC Execution Model Building Unaligned Vector Operands Idea: build an unaligned operand during register read Only one unaligned operand suffice for stencils Build the unaligned operand (i.e. VOPR x ) with two source regs base and extension 16x128-bit vector register file base = VR 1 , extension = VR 14 source offset VOPR x Naser Sedaghati (CSE @ Ohio State) StVEC: A Vector Instruction Extension PACT’11 10 / 24

  23. Enhancing Vector ISA with StVEC Execution Model Building Unaligned Vector Operands Idea: build an unaligned operand during register read Only one unaligned operand suffice for stencils Build the unaligned operand (i.e. VOPR x ) with two source regs base and extension 16x128-bit vector register file base = VR 1 , extension = VR 14 source offset VOPR x 0 X 1 , 0:4 ( aligned ) VR 1 Naser Sedaghati (CSE @ Ohio State) StVEC: A Vector Instruction Extension PACT’11 10 / 24

Download Presentation
Download Policy: The content available on the website is offered to you 'AS IS' for your personal information and use only. It cannot be commercialized, licensed, or distributed on other websites without prior consent from the author. To download a presentation, simply click this link. If you encounter any difficulties during the download process, it's possible that the publisher has removed the file from their server.

Recommend

Energy-efficient &amp; High-performance Energy-efficient &amp; High-performance Instruction Fetch

Energy-efficient &amp; High-performance Energy-efficient &amp; High-performance Instruction Fetch

Energy-efficient &amp; High-performance Energy-efficient &amp; High-performance Instruction Fetch using a Block-aware ISA Instruction Fetch using a Block-aware ISA Ahmad Zmily and Christos Kozyrakis Electrical Engineering Department Stanford

250 views • 23 slides
Day 3 Advanced Vector Architectures Session A: Vector Instruction Execution Pipelines Break

Day 3 Advanced Vector Architectures Session A: Vector Instruction Execution Pipelines Break

Day 3 Advanced Vector Architectures Session A: Vector Instruction Execution Pipelines Break Session B: Vector Flag Processing &amp; Vector Register Files Lunch Session C: Virtual Processor Caches Break Session D: Vector IRAM Vector

498 views • 22 slides
A Standard f A S tandard for or High Quality High Quality Instruction Instruction

A Standard f A S tandard for or High Quality High Quality Instruction Instruction

Charles Smith, Ph.D. Executive Director, David P. Weikart Center for Youth Program Quality #readyby21 A Standard f A S tandard for or High Quality High Quality Instruction Instruction Higherorderengagement

386 views • 36 slides
NOW Handout Page 1 1 Styles of Vector Architectures Components of Vector Processor Vector

NOW Handout Page 1 1 Styles of Vector Architectures Components of Vector Processor Vector

Alternative Model:Vector Processing EECS 252 Graduate Computer Vector processors have high-level operations that work on linear arrays of numbers: &quot;vectors&quot; Architecture SCALAR VECTOR (1 operation) (N operations) Lec 10

327 views • 10 slides
Getting the Performance Out Of Getting the Performance Out Of High Performance Computing High

Getting the Performance Out Of Getting the Performance Out Of High Performance Computing High

Getting the Performance Out Of Getting the Performance Out Of High Performance Computing High Performance Computing Jack Dongarra I nnovative Computing Lab University of Tennessee and Computer Science and Math Division Oak Ridge Nat ional

380 views • 13 slides
Efficient Software Implementation of Binary Field Arithmetic Using Vector Instruction Sets Diego

Efficient Software Implementation of Binary Field Arithmetic Using Vector Instruction Sets Diego

Efficient Software Implementation of Binary Field Arithmetic Using Vector Instruction Sets Diego F. Aranha Department of Computer Science University of Bras lia Joint work with Julio L opez and Darrel Hankerson and Francisco Rodr

528 views • 40 slides
Agenda Susan Gunderman Mimi Dyer Lenora Nyeste 1. Rigor, Relevance and High School Reinvention

Agenda Susan Gunderman Mimi Dyer Lenora Nyeste 1. Rigor, Relevance and High School Reinvention

Model Schools 06 High School Reinvention - Focus on Instruction High School Reinvention www.peterpappas.com ~ Focus on Instruction High School Social Studies Teacher K-12 Program Director Assistant Superintendent Senior Consultant

277 views • 16 slides
1 What Limits Performance? Stalls (Data Hazards) Data hazards Code Instruction depends on

1 What Limits Performance? Stalls (Data Hazards) Data hazards Code Instruction depends on

Instruction Scheduling Background: Pipelining Basics Last time Idea Register allocation Begin executing an instruction before completing the previous one Today Without Pipelining With Pipelining Instruction scheduling The

389 views • 7 slides
HASHI: An Application-Specific Instruction Set Extension for Hashing Oliver Arnold, Sebastian

HASHI: An Application-Specific Instruction Set Extension for Hashing Oliver Arnold, Sebastian

Technische Universitt Dresden HASHI: An Application-Specific Instruction Set Extension for Hashing Oliver Arnold, Sebastian Haas, Gerhard Fettweis, Benjamin Schlegel, Thomas Kissinger, Tomas Karnagel, Wolfgang Lehner Technische Universitt

388 views • 15 slides
Instruction Set 2 Architecting a vocabulary for the HW INSTRUCTION SET OVERVIEW 3 Instruction

Instruction Set 2 Architecting a vocabulary for the HW INSTRUCTION SET OVERVIEW 3 Instruction

1 EE 109 Unit 13 MIPS Instruction Set 2 Architecting a vocabulary for the HW INSTRUCTION SET OVERVIEW 3 Instruction Set Architecture (ISA) Defines the software interface of the processor and memory system Instruction set is the

915 views • 52 slides
PERFORMANCE OPTIMISATION Adrian Jackson adrianj@epcc.ed.ac.uk Hardware design Image from Colfax

PERFORMANCE OPTIMISATION Adrian Jackson adrianj@epcc.ed.ac.uk Hardware design Image from Colfax

PERFORMANCE OPTIMISATION Adrian Jackson adrianj@epcc.ed.ac.uk Hardware design Image from Colfax training material Pipeline Simple five stage pipeline: 1. Instruction fetch get instruction from instruction cache 2. Instruction decode

759 views • 44 slides
1 CPI Cycles per Instruction Instruction Classes We can have different CPIs for different

1 CPI Cycles per Instruction Instruction Classes We can have different CPIs for different

Performance Introduction Many factors impact performance: Technology: basic circuit speed (clock speed, usually in MHz, now in GHz - billions of cycles per second) process technology (# of transistors per chip) Organization:

138 views • 3 slides
ARM Advanced RISC Machines The ARM Instruction Set The ARM Instruction Set - ARM University

ARM Advanced RISC Machines The ARM Instruction Set The ARM Instruction Set - ARM University

ARM Advanced RISC Machines The ARM Instruction Set The ARM Instruction Set - ARM University Program - V1.0 1 Processor Modes * The ARM has six operating modes: User (unprivileged mode under which most tasks run) FIQ (entered when a high

1.02k views • 75 slides
ATSS PROCESS CORE INSTRUCTION, INTERVENTION SELECTION, EXTENSION AND PROGRESS MONITORING ATSS

ATSS PROCESS CORE INSTRUCTION, INTERVENTION SELECTION, EXTENSION AND PROGRESS MONITORING ATSS

ATSS PROCESS CORE INSTRUCTION, INTERVENTION SELECTION, EXTENSION AND PROGRESS MONITORING ATSS is a Process A process to analyze data A process to determine student strengths and need A process to make a plan to respond to strength

680 views • 18 slides
Extension, Abbreviation and Refinement - Identifying High-Level Dependence Structures Using

Extension, Abbreviation and Refinement - Identifying High-Level Dependence Structures Using

Extension, Abbreviation and Refinement - Identifying High-Level Dependence Structures Using Slice-Based Dependence Analysis Zheng Li CREST, Kings College London, UK Overview Motivation Three combination techniques Extension

694 views • 33 slides
1 Components of a Vector Processor Cray- 1 Block Scalar CPU: regist ers, dat apat hs,

1 Components of a Vector Processor Cray- 1 Block Scalar CPU: regist ers, dat apat hs,

Vector Processors CS252 I nit ially developed f or super -comput ing applicat ions, Graduate Computer Architecture t oday impor t ant f or mult imedia. Lecture 20 Vect or pr ocessor s have high- level oper at ions t hat Vector

667 views • 9 slides
Electromagnetic Form Factors through Parity-Expanded Variational Analysis Finn M. Stokes Waseem

Electromagnetic Form Factors through Parity-Expanded Variational Analysis Finn M. Stokes Waseem

Electromagnetic Form Factors through Parity-Expanded Variational Analysis Finn M. Stokes Waseem Kamleh, Derek B. Leinweber and Benjamin J. Owen Centre for the Subatomic Structure of Matter Finn M. Stokes (CSSM) Parity-Expanded Variational

1k views • 62 slides
Problem Dicusssion Part 2: Some more problems Lucca Siaudzionis and Jack Spalding-Jamieson

Problem Dicusssion Part 2: Some more problems Lucca Siaudzionis and Jack Spalding-Jamieson

Problem Dicusssion Part 2: Some more problems Lucca Siaudzionis and Jack Spalding-Jamieson 2020/03/19 University of British Columbia Announcements A4 is now due Wednesday March 25th. 1 Maximum Area Rectangle Find the maximum area of a

536 views • 31 slides
Directional recurrence, ergodicity, and weak mixing Ay se S ahin DePaul University June

Directional recurrence, ergodicity, and weak mixing Ay se S ahin DePaul University June

Motivation for directional dynamics Defining directional properties Directional recurrence Examples of R T Directional ergodicity and weak mixing The correct definitions Studying W M T Directional recurrence, ergodicity, and weak mixing Ay

858 views • 48 slides
Threatened by a Great Opportunity: Disruptive Innovation in Formal Verification John Rushby

Threatened by a Great Opportunity: Disruptive Innovation in Formal Verification John Rushby

Threatened by a Great Opportunity: Disruptive Innovation in Formal Verification John Rushby Computer Science Laboratory SRI International Menlo Park, California, USA John Rushby, SR I Verify06: Disruptive Innovation1 Since The

856 views • 40 slides
Basic Search Algorithms Tsan-sheng Hsu tshsu@iis.sinica.edu.tw

Basic Search Algorithms Tsan-sheng Hsu tshsu@iis.sinica.edu.tw

Basic Search Algorithms Tsan-sheng Hsu tshsu@iis.sinica.edu.tw http://www.iis.sinica.edu.tw/~tshsu 1 Abstract The complexities of various search algorithms are considered in terms of time, space, and cost of the solution paths. Systematic

956 views • 74 slides
XPANDER: TOWARDS OPTIMAL-PERFORMANCE DATACENTERS Asaf Valadarsky (Hebrew University) Gal Shahaf

XPANDER: TOWARDS OPTIMAL-PERFORMANCE DATACENTERS Asaf Valadarsky (Hebrew University) Gal Shahaf

XPANDER: TOWARDS OPTIMAL-PERFORMANCE DATACENTERS Asaf Valadarsky (Hebrew University) Gal Shahaf (Hebrew University) Michael Dinitz (Johns Hopkins University) Michael Schapira (Hebrew University) DESIGNING A DATACENTER ARCHITECTURE Network

2.85k views • 26 slides
High Dimensional Expanders Luis Kumanduri MIT 1 / 3 What is an expander? Definition Let X be a

High Dimensional Expanders Luis Kumanduri MIT 1 / 3 What is an expander? Definition Let X be a

High Dimensional Expanders Luis Kumanduri MIT 1 / 3 What is an expander? Definition Let X be a d -dimensional simplicial complex. X is an -topological expander if for every continuous F : X R d , there is a point p R d so that F

212 views • 3 slides
Lossless Expander Graphs in Compressive Sensing Abbas Kazemipour MAST Group Meeting University

Lossless Expander Graphs in Compressive Sensing Abbas Kazemipour MAST Group Meeting University

Lossless Expander Graphs in Compressive Sensing Abbas Kazemipour MAST Group Meeting University of Maryland. College Park kaazemi@umd.edu October 22, 2015 Abbas Kazemipour (UMD) Expanders October 22, 2015 1 / 8 Overview 1 Introduction

513 views • 19 slides

More recommend