Stress and Characterization Strategies to Assess Oxide Breakdown in - - PowerPoint PPT Presentation

Stress and Characterization Strategies to Assess Oxide Breakdown in High-Voltage GaN Field-Effect Transistors

Shireen Warnock and Jesús A. del Alamo

Microsystems Technology Laboratories (MTL) Massachusetts Institute of Technology (MIT)

Outl tline

• Motivation & Challenges
• Time-Dependent Dielectric Breakdown (TDDB)

Experiments:

‒Current-Voltage ‒Capacitance-Voltage

• Conclusions

2

Motivation

• GaN Field-Effect Transistors (FETs) promising for high-voltage

power applications

• Many challenges before transistors ready for deployment:

3

Motivation

Inverse piezoelectric effect

• J. A. del Alamo, MR 2009
• GaN Field-Effect Transistors (FETs) promising for high-voltage

power applications

• Many challenges before transistors ready for deployment:

4

Motivation

• GaN Field-Effect Transistors (FETs) promising for high-voltage

power applications

• Many challenges before transistors ready for deployment:

Inverse piezoelectric effect

• J. A. del Alamo, MR 2009

Current collapse

• D. Jin, IEDM 2013

5

Motivation

Inverse piezoelectric effect

• J. A. del Alamo, MR 2009

Current collapse

• D. Jin, IEDM 2013

VT instability

• D. Johnson, TED 2013
• GaN Field-Effect Transistors (FETs) promising for high-voltage

power applications

• Many challenges before transistors ready for deployment:

6

Motivation

Inverse piezoelectric effect

• J. A. del Alamo, MR 2009

Current collapse

• D. Jin, IEDM 2013

Oxide reliability

VT instability

• D. Johnson, TED 2013
• GaN Field-Effect Transistors (FETs) promising for high-voltage

power applications

• Many challenges before transistors ready for deployment:

7

Time me-Dep epen enden ent D Dielectr tric ic B Brea eakdown

• High gate bias → defect generation → catastrophic oxide

breakdown

• Often dictates lifetime of chip
• D. R. Wolters, Philips J. Res. 1985
• T. Kauerauf, EDL 2005

Typical TDDB experiments: Si high-k MOSFETs Gate material melted after breakdown

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Challenges to study T TDDB in GaN F FET ETs

• AlGaN/GaN metal-insulator-

semiconductor high electron mobility transistors (MIS-HEMTs)

• Gate stack has multiple layers &

interfaces

→ Uncertain electric field distribution → Many trapping sites

• Complex dynamics involved

→ Unstable and fast changing VT

• P. Lagger, TED 2014

stress time ↑

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TDDB Ex Experi riments: Curr rrent-Vo Voltage

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Ga GaN N MIS-HEMTs for T TDDB DB stud udy

GaN MIS-HEMTs from industry collaboration: depletion-mode

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Classic T TDDB Ex Experi riment

Constant gate voltage stress experiment:

• Experiment gives time to breakdown and shows

generation of stress-induced leakage current (SILC)

• Little other insight gained from measurement

trapping SILC Hard breakdown

tBD

IG

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Visualizi zing TDDB Statistics

TDDB uniqueness: Weibull distribution of time to breakdown

• As VGstress ↑, tBD ↓
• Parallel distributions for different VGstress

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TDDB w with P Peri riodic Characteri rization

Pause TDDB stress and sweep transfer characteristics at VDS=0.1 V

• Large VT shift → trapping in oxide or AlGaN
• Immediate S degradation → interface state generation early in

experiment

14

Validity ty of Characteri rization Ap Approach

Compare statistics for standard and interrupted schemes Same statistics for both schemes → characterization is benign

15

St Step ep-Stress ss T TDD DDB

• Step-stress to examine early stages of degradation
• Step VGstress in 0.5 V increments until breakdown
• Low VGstress: IG ↓ ⇒ trapping
• High VGstress: IG ↑ ⇒ SILC

VDS=0 V

16

St Step ep-Stress ss T TDD DDB

Transfer characteristics during Step-Stress TDDB

• S and VT degradation is progressive
• At VGstress ~12.5 V, ΔVT < 0 (red lines)

‒ Sudden increase in S, appearance of SILC→ interface state generation

VDS=0.1 V

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TDDB Ex Experi riments: Capacitance-Vo Voltage

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C-V Characteri rization

• At VGS>1 V, conduction band of GaN cap starts being

populated

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C-V Characteri rization

TDDB characterization takes place here

• TDDB characterized in regime where GaN cap is populated

with electrons

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Consta tant nt VGstre

ress TDDB

• As stress time ↑

→ CGG ↑ → Frequency dispersion ↑

• Consistent with trap creation and trapping

‒ In oxide and/or at MOS interface

CGG vs. stress time in 5 devices at 5 different frequencies:

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St Step ep-Stress ss T TDD DDB

• Moderate VGstress → CGG ↓ ⇒ trapping in AlGaN

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St Step ep-Stress ss T TDD DDB

• Moderate VGstress → CGG ↓ ⇒ trapping in AlGaN
• High VGstress → CGG ↑ ⇒ trap generation in oxide

CGG changes shape

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Conclusions

• Developed methodology to study TDDB in GaN MIS-

HEMTs

• TDDB behavior consistent with Si MOSFETs:

‒ Weibull distribution ‒ SILC before breakdown

• For moderate gate voltage stress:

‒ ΔVT > 0 ‒ IG ↓

• Beyond critical value of VGstress:

‒ ΔVT < 0 ‒ Sudden ΔS ↑ ‒ Capacitance frequency dispersion ↑

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Conclusions

• Developed methodology to study TDDB in GaN MIS-

HEMTs

• TDDB behavior consistent with Si MOSFETs:

‒ Weibull distribution ‒ SILC before breakdown

• For moderate gate voltage stress:

‒ ΔVT > 0 ‒ IG ↓

• Beyond critical value of VGstress:

‒ ΔVT < 0 ‒ Sudden ΔS ↑ ‒ Capacitance frequency dispersion ↑ Consistent with electron trapping

25

Conclusions

• Developed methodology to study TDDB in GaN MIS-

HEMTs

• TDDB behavior consistent with Si MOSFETs:

‒ Weibull distribution ‒ SILC before breakdown

• For moderate gate voltage stress:

‒ ΔVT > 0 ‒ IG ↓

• Beyond critical value of VGstress:

‒ ΔVT < 0 ‒ Sudden ΔS ↑ ‒ Capacitance frequency dispersion ↑ Consistent with electron trapping Onset of trap generation in oxide/at MOS interface

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Acknowled edgem emen ents

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Qu Ques estion

• ns?

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