Status of GRL Yun-Tsung Lai KEK ytlai@post.kek.jp 32nd B2GM - - PowerPoint PPT Presentation

Status of GRL

2019/02/05 1 Yun-Tsung Lai (KEK) @ 32nd B2GM

Yun-Tsung Lai

KEK

ytlai@post.kek.jp

32nd B2GM February 5, 2019

• Jitter between each sub-triggers’ input and latency study.
• GRL logic confirmation with cosmic data.
• B2L suppress mode for TRG boards.

Outline

2 Yun-Tsung Lai (KEK) @ 32nd B2GM 2019/02/05

• CDC: first 2D track input in this event.
• Uncertainty of KLM latency will be reduced after their FE firmware update.

Jitter between inputs

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CDCECL: 300~1000 ns CDCKLM: -700~1500 ns CDCTOP: 400~1300 ns ECLL1: 818~1151 ns

• trgdelay = 11 (32ns clk)
• Offset from the right edge

to L1 trg: ~13*32 ns

• Waiting to KLM input to fix their latency.
• For GRL  GDL link, CDC 2D associated bits will still use GTH.

For the other bits associated with outer detectors will use LVDS. Latency is ~8 ns.

• Latency of 3D and NN will be checked soon.

Jitter between inputs (cont’d)

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CDCECL: 300~1000 ns CDCKLM: -700~1500 ns CDCTOP: 400~1300 ns ECLL1: 818~1151 ns L1: 1500~1800 ns CDC drift time: 500ns 750 1500 First 2D track ECL input GRLGDL latency: ~450 ns Latency limit in GRL (GTH) Latency limit in GRL (LVDS)

• All bits are correct now.

– Matched, and matched with 2 GeV. – Photon: 1 GeV and 2 GeV.

Matching logic: CDC-ECL

5 Yun-Tsung Lai (KEK) @ 32nd B2GM 2019/02/05

𝜚 map of CDC and ECL expected result firmware readout

firmware logic

• ffline check

consistency check

• CDC-TOP case looks fine.
• CDC-KLM case looks still not so consistent. Under investigation.

– Some of the N = 1 in firmware is actually N = 2. – No angular dependency. – Large latency events might be a reason: The input is too late for the logic and the

• utput is out of B2L window.

– Will tune the persistor size to check.

Matching logic: CDC-TOP and CDC-KLM

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• ETM is using a window collect TC info within

two dataclks for clustering to avoid missing TC at edge. – Possible problem: an energetic TC is counted twice, then causes two similar clusters in continuous dataclks.

• Check with cosmic run r2888.

– Energy, theta, and phi difference of each 1st clk and 2nd clk combination.

• We can see a peak at difference = 0 for energy, theta, and phi.

Check on ECL cluster output

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1st clk 2nd clk

• For Δ𝐹 = 0:

– With Δ𝜄 = 0: 94.3% – With Δ𝜚 = 0: 93.3% – With Δ𝜄 = 0 & Δ𝜚 = 0 : 93.1%

• For Δ𝜄 = 0:

– With Δ𝐹 = 0: 31.5% – With Δ𝜚 = 0: 51.6% – With Δ𝐹 = 0 & Δ𝜚 = 0 : 31.1%

• For Δ𝜚 = 0:

– With Δ𝐹 = 0: 42.2% – With Δ𝜄 = 0: 69.7% – With Δ𝐹 = 0 & Δ𝜄 = 0 : 42.1%

Relation between variables

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 For two clusters in two continuous clks with the same energy, it is very likely for them to be nearby.

• For Δ𝐹 = 0:

– Not necessary to be an energetic cluster?

Relation between variables (cont’d)

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• B2L of TRG: snapshot on waveform within a window.  Too many zero.
• CB: To handle delay and width of data window.

– EX: GRL uses 1k*24 clk. CB is 1k*512 clk.

• Parallel DAQ buffers: To handle 2 events with very close L1trg into pipeline.

– EX: GRL uses 1k*24 clk*N (N = 12)

B2L in TRG

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delay L1trg width of data window Parallel DAQ buffer Serialization, then into b2l_transmitter

• GRL: timing/waveform is not so important due to latency difference between inputs.

– Better to record only 1 bit for “On or Off” info: b2b, opening, N(track…). – Integrate those signals on time.

• Original idea: take a window with a delay w.r.t L1trg.
• Suppress mode: take one clock with a (no) delay w.r.t L1trg.

– Only need to change the parameter width to 1. – The size of CB (Block RAM usage) can be slightly reduced. (512  ~32) – The size of DAQ buffer can be reduced. (1k*24 clk*N  1k*1 clk*N)

B2L suppress mode in TRG

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L1trg Parallel DAQ buffer delay (could be 0) width = 1 Serialization, then into b2l_transmitter

• b2lwe: valid signal to b2l core logic. Synchronized to the serialized data.
• b2lpause: to distinguish header and data.
• b2lout: Serialized 1k (1clk) data in 8 bits
• Original CB: 1k*24 clocks in total
• Suppress mode: dataout: 1k*24  1k
• b2lwe/b2lpause/b2lout: Correctly behave as this change.

ISIM test

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• 1b On/Off information: Persist it up to when L1trg arrives.
• For the other cases, a signal would store multiple information in different clocks.

– EX: ETM sends cluster output to GRL in 1~2 dataclk. – Have to prepare enough bandwidth to persist those signals parallelly.

Utilization

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• GRL firmware: 1k*24 clks  1k*1 clk
• No problem in local run.
• 1k in each event:

Firmware test result

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• By using cosmic data after phase2, matching logics in GRL (CDC - ETM, TOP,

KLM) are mostly confirmed to be working. Latency are measured. – Most of the trg bits are ready.

• B2L suppress mode is tested with latest version of CB.

– Full GRL firmware with it is ready. – Hope to test it in this week to see the data size reduction, trg dead time, and busy.

• Short-term schedule for GRL work:

– Test firmware with B2L suppress mode for DAQ check: This week. – Unpacker and data analysis for suppress mode: ~ End of Feb. – 3D/NN counting with z0 cut: Waiting now. Before phase3? – Firmware update for short tracking + TSF GTX link: Middle of Mar. After TSF work is completed. – Unpacker and data analysis with short tracking: Early phase3. – Official unpacker and DQM.

Summary & To do

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