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Statistical Timing Analysis Statistical Timing Analysis g g y y Considering Spatially and Considering Spatially and Temporally Correlated Dynamic Temporally Correlated Dynamic Temporally Correlated Dynamic Temporally Correlated Dynamic

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SLIDE 1

Statistical Timing Analysis Statistical Timing Analysis g y g y Considering Spatially and Considering Spatially and Temporally Correlated Dynamic Temporally Correlated Dynamic Temporally Correlated Dynamic Temporally Correlated Dynamic Power Supply Noise Power Supply Noise

Takashi Enami Shinyu Ninomiya Masanori Hashimoto Takashi Enami Shinyu Ninomiya Masanori Hashimoto

  • Dept. Information Systems Engineering, Osaka Univ., Japan

{ i t k hi i i hi h i t }@i t k j {enami.takashi, ninomiya.shinyu, hasimoto}@ist.osaka-u.ac.jp

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SLIDE 2

Agenda

  • Background and objective
  • Statistical modeling of power supply noise
  • SSTA with statistical model of power supply noise

SSTA with statistical model of power supply noise

  • Experimental results

C l i

  • Conclusion

2008/04/16 ISPD 2008 2

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SLIDE 3

Background

Voltage drop at power wire.

  • Power supply noise is becoming more influential on timing

due to

– increasing current consumption, – decreasing power supply voltage.

Demand for timing analysis considering

2008/04/16 ISPD 2008 3

power supply noise.

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SLIDE 4

Objective

  • Conventional analysis method

– Dynamic analysis

  • Analysis with test patterns.

=> Combination space of test patterns is tremendous => Combination space of test patterns is tremendous.

– Static analysis

  • Analysis with constant voltage drop.

y g p => Irrelevant voltage drop leads to optimistic or excessively pessimistic estimation.

Exact worst-case delay cannot be obtained practically.

Propose a statistical timing analysis method

2008/04/16 ISPD 2008 4

that gives reasonable worst-case timing.

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SLIDE 5

Difficulties of noise aware timing analysis affect gate delay

  • Cell position (spatial)

affect gate delay.

  • Switching timing (temporal)

B

e A t d l (A) > spatial difference A d l (t ) > d l (t ) temporal difference

A

Voltage B t1: delay(A) > delay(B) t2: delay(A) < delay(B) A: delay(t1) > delay(t2) B: delay(t1) < delay(t2) Time t1 t2 delay(B)

Position of critical paths and spatial and temporal variation

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p p must be considered simultaneously.

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SLIDE 6

Proposed approach (Overview)

including spatial and

Estimate the worst-case

temporal variation

  • f power supply noise

Statistical model

Voltage

delay.

bility

model Circuit

Time V Probab

SSTA structure Power supply noise

Delay

Delay distribution

2008/04/16 ISPD 2008 6

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SLIDE 7

Agenda

  • Background and objective
  • Statistical modeling of power supply noise
  • SSTA with statistical model of power supply noise

SSTA with statistical model of power supply noise

  • Experimental results

C l i

  • Conclusion

2008/04/16 ISPD 2008 7

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SLIDE 8

Modeling flow

Power supply noise

Spatial and temporal division.

Power variables

1 Gaussianization: if necessary

  • 1. Gaussianization: if necessary

improve Gaussianity of the variables.

  • 2. Orthogonalization:

Statistical model

g transform the correlated variables into the uncorrelated variables.

2008/04/16 ISPD 2008 8

Statistical model

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SLIDE 9

Spatial and temporal division

remove spatial and temporal continuity for variable assignment

1 Cycle

for variable assignment

  • ltage

Vo

V V V V V

Time

Vx,y,3 Vx,y,1 Vx,y,2 Vx,y,3 Vx,y,1

ex) divide a clock cycle into 3 time spans. choose a representative value

spatial division temporal division

) y p use average voltage in each span

2008/04/16 ISPD 2008 9

choose a representative value for each partition. use average voltage in each span.

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SLIDE 10

Assigning variables and obtaining distribution

ty

Vx,y,1 1 Cycle

Probabilit

different clock cycle Voltage

Voltage P y

Vx,y,2 different clock cycle => different sample V

Vx y 3 Vx y 1 Vx y 2 Vx y 3 Vx y 1 Probability

Time

Vx,y,3 Vx,y,1 Vx,y,2 Vx,y,3 Vx,y,1 Voltage P y

Vx,y,3 calculate average, standard deviation and

Data set of power variables

Probability

standard deviation and correlation coefficient

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Voltage P

can model spatial and temporal variation.

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SLIDE 11

Correlation of power variables

1 cycle tage ltage Volt

spatial correlation

  • ltage Vo

Time

Voltage drop tends to be similar.

Time

temporal correlation Voltage drop lasts awhile.

Time Vo

g p g p spatial correlation temporal correlation

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spatial correlation temporal correlation

Correlation of power variables is strong.

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SLIDE 12

Correlation’s effect on delay

Correlation between variables affects delay distribution.

V1,V2: ex) SUM operation

  • bability

no correlation V1,V2: positive correlation Delay Pro positive correlation V1 V2

Delay calculation considering correlation i i i bl is inevitable.

2008/04/16 ISPD 2008 12

Computationally expensive.

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SLIDE 13

Orthogonalization

  • Orthogonalization by principal component

analysis (PCA)

– Delay calculation considering correlation is facilitated [1]. – Compact statistical model is derived when strong correlation exists. – Compatibility with SSTA developed for manufacturing variability [1] variability [1].

  • zi
  • μi

: original variable : average of zi

  • σi
  • λj

: standard deviation of zi : jth largest eigenvalue

compac t

  • eij
  • pcj

: jth eigenvector corresponding to zi : jth principal component (PC)

[1] H Chang et al “Statistical Timing Analysis

2008/04/16 ISPD 2008 13

p j

  • k, k’

jt p c pa co po e t ( C) : number of PCs

[1] H. Chang, et. al., Statistical Timing Analysis Under Spatial Correlations,” IEEE TCAD,

  • Vol. 24, No. 9, Sep. 2005.
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SLIDE 14

Gaussianization

PCA assumes Gaussian distribution. S i bl i ht b diff t f G i Some variables might be different from Gaussian.

improve Gaussianity of the variables before PCA

Box-Cox transformation

Λ: Every variable has h i l i di id ll

improve Gaussianity of the variables before PCA.

transformation

the optimum value individually.

  • riginal distribution

transformed distribution

Box-Cox Box Cox transformation

2008/04/16 ISPD 2008 14

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SLIDE 15

Agenda

  • Background and objective
  • Statistical modeling of power supply noise
  • SSTA with statistical model of power supply noise

SSTA with statistical model of power supply noise

  • Experimental results

C l i

  • Conclusion

2008/04/16 ISPD 2008 15

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SLIDE 16

Gate delay calculation

receiver side canonical gate delay model id i l i receiver side considering power supply noise. driver side

σV** : standard deviation of V**

: sensitivity of V** to d*

e(V**),j : jth eigenvector

corresponding to V**

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How are these parameters(μr, Ar,j) decided?

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SLIDE 17

Parameter calculation

  • Parameters of canonical delay model

must consider not only cell position but also switching timing,

– Parameters are set based on arrival time. If switching timing crosses over

μr ,ar,j 1 cycle

If switching timing crosses over the boundary of two time spans. => calculate weighted-average

Time

g g

  • f two spans.

arrival time arrival time

2008/04/16 ISPD 2008 17

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SLIDE 18

Agenda

  • Background and objective
  • Statistical modeling of power supply noise
  • SSTA with statistical model of power supply noise

SSTA with statistical model of power supply noise

  • Experimental results

Accuracy of proposed SSTA – Accuracy of proposed SSTA – SSTA with reduced model SSTA id i l i d – SSTA considering power supply noise and manufacturing variability

Conclusion

  • Conclusion

2008/04/16 ISPD 2008 18

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SLIDE 19

Experimental conditions

  • noise generators,

– two circuits,

  • FPU[2] (90nm process, 39k gates),
  • tiny64 processor[2] (90nm process 20k gates)

tiny64 processor[2] (90nm process, 20k gates),

– size: 1mm x 1mm, – input vector: random, 2000 clock cycles,

  • circuits for timing analysis,

– ISCAS85 (5 circuits), – 64-bit multiplier, – ALU, H tree (evaluation of clock jitter)

FPUの電源網

– H-tree (evaluation of clock jitter),

2008/04/16 ISPD 2008 19

[2] OPENCORES.ORG, http://www.opencores.org/.

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SLIDE 20

Procedure of accuracy evaluation

compare proposed SSTA and Monte Carlo STA (MC) using the same noise information given to PCA using the same noise information given to PCA.

delay distribution (MC) power supply noise (MC)

MC statistical model comparison

modeling

proposed SSTA statistical model

delay distribution (proposed SSTA)

proposed SSTA

(p p )

  • SSTA includes errors that originate from

– discretization,

2008/04/16 ISPD 2008 20

– PCA for incomplete Gaussian distribution, – SSTA operation.

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SLIDE 21

Accuracy of proposed SSTA

|SSTA MC|

circuit # cells

|SSTA – MC| MC avg (%) sd (%) c432 232 0.478 4.21

  • Proposed SSTA estimates

the delay accurately. E ti ti

c1355 329 1.27 29.4 c1908 387 0.472 24.1 c6288 3382 0.370 9.15

  • Estimation errors

without Box-Cox transformation (avg: 0 465% sd: 14 4%)

c6288 3382 0.370 9.15 c7552 2070 0.172 13.8 multiplier 41629 0.0969 7.23 ALU 14655 0.216 2.87

(avg: 0.465%, sd: 14.4%), => non-Gaussianity was not significant but

ALU 14655 0.216 2.87 H-tree 7 0.576 10.8 average

  • 0.456

12.7

Box-Cox transformation improved results slightly.

noise generator: FPU spatial division number: 10x10 temporal division number: 10

2008/04/16 ISPD 2008 21

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SLIDE 22

Evaluation of variable reduction

Evaluate accuracy and CPU time with th d d b f i i l t (PC ) the reduced number of principal components (PCs).

spatial division number: 10x10 temporal division number: 10 noise generator: tiny64 circuit: multiplier

# PCs avg (ps) sd (ps) CPU time (ms) reduction rate

  • f CPU time (%)

spatial division number: 10x10 temporal division number: 10 => total 2000 variables (power + ground) @ Opteron 2.4GHz

g (p ) (p ) (ms)

  • f CPU time (%)

1 1843 0.384 164 98.6 2 2708 3.16 166 98.6

# PCs

4 2708 3.71 180 98.5 8 2708 4.07 205 98.3

# PCs reduction

16 2708 4.09 238 98.0 2000 2708 4.09 11800

2008/04/16 ISPD 2008 22

reduce CPU time largely with little loss of accuracy.

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SLIDE 23

SSTA result both for power supply noise and manufacturing variability

Proposed SSTA has a compatibility with SSTA developed for manufacturing variability developed for manufacturing variability. => can perform SSTA considering manufacturing and supply voltage fluctuation simultaneously. supply voltage fluctuation simultaneously.

noise generator: FPU circuit: multiplier circuit: multiplier spatial division number: 10x10 temporal division number: 10 Vth variation: σ = 25mv

SSTA considering both variabilities

2008/04/16 ISPD 2008 23

SSTA considering both variabilities has a possibility to reduce timing margin.

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SLIDE 24

Conclusion

  • Proposed SSTA can consider dynamic power

supply noise with PCA.

– Errors of proposed SSTA

  • average: 0.456%,
  • standard deviation: 12.7%.

SSTA ith th ti l d l d d CPU ti – SSTA with the partial model reduced CPU time more than 98% almost without loss of accuracy. Proposed SSTA can be performed considering – Proposed SSTA can be performed considering manufacturing and supply voltage fluctuation simultaneously. simultaneously.

2008/04/16 ISPD 2008 24

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SLIDE 25

2008/04/16 ISPD 2008 25

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SLIDE 26

Calculation with switching transition

calculate weighted-average of the parameters di t i t d t t t iti ti i corresponding to input and output transition timing.

Span #(m) Span #(m+1) μr ,ar,j

  • 1. estimate tO with the use of μrm.

Time ΔtI ΔtO

  • 2. calculate weighted-average

Time switching term (μrm)

I O

tI tO

based on ΔtI and ΔtO . average

g (μ m)

coefficient

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Circuit delay is calculated according to conventional SSTA.

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SLIDE 27

Clock Skew Analysis

Easily perform by application of clock jitter analysis.

∑

+ =

' , 1 1 1 k j j pc

a jitter μ

∑

=1 j j j

∑

' k

ji

∑

=

+ =

1 , 2 2 2 j j j pc

a jitter μ

( )

( )

⎬ ⎫ ⎨ ⎧ + ∑

' k

pc a a skew μ μ

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( )

( )

⎭ ⎬ ⎩ ⎨ − + − =

∑

=1 , 2 , 1 2 1 2 , 1 j j j j

pc a a skew μ μ

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SLIDE 28

Adaptive spatial discretization

Power supply noise has

heavily fluctuating area.

Power supply noise has

calm area.

=> fine division => coarse division

2008/04/16 ISPD 2008 28

Adaptive discretization of FPU noise. Spatial distribution of FPU noise (average).