Software-Managed TRANSLATION Address Translation Bruce Jacob - - PDF document

SOFTWARE- MANAGED ADDRESS TRANSLATION Bruce Jacob University of Michigan

Software-Managed Address Translation

Bruce Jacob and Trevor Mudge Advanced Computer Architecture Lab University of Michigan OUTLINE:

• Background & Motivation
• Softvm Design
• Experiments & Results

ADVANCED COMPUTER ARCHITECTURE LAB

SOFTWARE- MANAGED ADDRESS TRANSLATION Bruce Jacob University of Michigan

Historical Perspective

MIPS:

• HW page-table-walking unnecessary

SPUR:

• HW storage for PTEs unnecessary

VMP:

• Software-controlled caches work

CONCLUSION: Can get rid of TLB altogether

SOFTWARE- MANAGED ADDRESS TRANSLATION Bruce Jacob University of Michigan

TLB Architecture

Virtual Page Number Page Offset PFN VPN TLB (CAM) Cache Block (Data) P-Tag DIRECT-MAPPED CACHE Match? Pr Protection Violation? AND CACHE DATA

SOFTWARE- MANAGED ADDRESS TRANSLATION Bruce Jacob University of Michigan

TLB Miss

CPU CACHE

NO DATA

TLB

TLB Miss

Index Index Offset BASE Root Table User Table Page Frame Virtual Address

SOFTWARE- MANAGED ADDRESS TRANSLATION Bruce Jacob University of Michigan

SOFTVM Architecture

CACHE MISS EXCEPTION V-Tag Cache Block (Data) DIRECT-MAPPED CACHE Match? Pr AND Protection Violation? CPU CACHE DATA

SOFTWARE- MANAGED ADDRESS TRANSLATION Bruce Jacob University of Michigan

SOFTVM Miss

CPU CACHE TAGS

CACHE MISS

Index Index Offset BASE Root Table User Table Page Frame Virtual Address CACHE DATA PHYSICAL ADDR PHYSICAL ADDR PHYSICAL & VIRTUAL ADDR

SOFTWARE- MANAGED ADDRESS TRANSLATION Bruce Jacob University of Michigan

Cost of Software Solution

Cost to handle TLB Miss: ~12 cycles

• Build PA & Load RPTE

Build PA & Load UPTE Insert UPTE into TLB Retry Load Cost to handle Cache Miss: ~15 cycles

• Build PA & Load RPTE

Build PA & Load UPTE Prepare caches for USER-DATA Build PA & Load USER-DATA Retry Load

SOFTWARE- MANAGED ADDRESS TRANSLATION Bruce Jacob University of Michigan

Cost vs. Cache Size

1M 2M 4M 2K 4K 8K 16K 32K 64K 128 256 512 Cache Size (combined) 30 60 90 120 150 180 Hit Rate and Cycles per Cache Miss 0.0 0.2 0.4 0.6 0.8 1.0 1.2 SOFTVM Overhead (CPI) D-CACHE HIT RATE I-CACHE HIT RATE COST PER CACHE MISS COST PER INSTRUCTION

SOFTWARE- MANAGED ADDRESS TRANSLATION Bruce Jacob University of Michigan

Experiments

Modified 32-BIT PowerPC Architecture, MIPS-like Page Table Trace-Driven Simulations:

• L1 Cache (20):

2—256 KBytes

• L2 Cache (100):

1, 2, 4 MBytes

• Linesizes:

16—128 Bytes RESULTS:

• Softvm:

0.1 to 5% Overhead

• Mach+MIPS:

5 to 10% Overhead

• Ultrix+MIPS:

2% Overhead

SOFTWARE- MANAGED ADDRESS TRANSLATION Bruce Jacob University of Michigan

Results

L1 Caches: 16/16KB D/I, 32-byte linesize L2 Caches: 64-byte linesize

GCC VORTEX IJPEG 512KB 1MB 2MB L2 Data Cache Size 0.000 0.010 0.020 0.030

DATA-SIDE

VORTEX GCC IJPEG 512KB 1MB 2MB L2 Instruction Cache Size

INSTRUCTION-SIDE

SOFTWARE- MANAGED ADDRESS TRANSLATION Bruce Jacob University of Michigan

Potential Problem: STREAM

MULTIMEDIA HAS NO TEMPORAL LOCALITY WORST-CASE SCENARIO: Take an exception for every cache line SOLUTIONS:

• Prefetch buffers
• Prefetch into L2 cache
• Provided unmapped regions to user

SOFTWARE- MANAGED ADDRESS TRANSLATION Bruce Jacob University of Michigan

Design Considerations

LARGE VIRTUAL CACHES: Synonym Problem SOLUTION: Segmentation

• r

Large ASIDs w/ Flat Address Space DRAWBACK: Increases size of cache tags

SOFTWARE- MANAGED ADDRESS TRANSLATION Bruce Jacob University of Michigan

Conclusions

TLB Elimination is Possible Cycle Time can DECREASE Performance can INCREASE Support for Multimedia Possible Software-Managed: FLEXIBILITY

ADVANCED COMPUTER ARCHITECTURE LAB