Slot-Level Time-Triggered Scheduling on COTS Multicore Platform with - - PowerPoint PPT Presentation

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Slot-Level Time-Triggered Scheduling on COTS Multicore Platform with - - PowerPoint PPT Presentation

May 29, 2023 133 likes •690 views

Slot-Level Time-Triggered Scheduling on COTS Multicore Platform with Resource Contentions Ankit Agrawal * , Gerhard Fohler * , Jan Nowotsch , Sascha Uhrig , and Michael Paulitsch * TU Kaiserslautern , Airbus Group Innovations

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SLIDE 1

Slot-Level Time-Triggered Scheduling

  • n COTS Multicore Platform

with Resource Contentions ∆

Ankit Agrawal *, Gerhard Fohler *, Jan Nowotsch §, Sascha Uhrig §, and Michael Paulitsch ǂ

* TU Kaiserslautern ,§ Airbus Group Innovations ,

and ǂ Thales Austria GmbH

April 12, 2016 1 WiP session RTAS 2016 ∆ Work supported by ARTEMIS project 621429 EMC2

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SLIDE 2

Motivation

April 12, 2016 WiP session RTAS 2016 2

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SLIDE 3
  • Shift to COTS multicore

platforms

Motivation

April 12, 2016 WiP session RTAS 2016 2

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SLIDE 4
  • Shift to COTS multicore

platforms

– Benefits: SWaP, performance/price ratio

Motivation

April 12, 2016 WiP session RTAS 2016 2

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SLIDE 5
  • Shift to COTS multicore

platforms

– Benefits: SWaP, performance/price ratio

  • Time-triggered (TT)

systems

Motivation

April 12, 2016 WiP session RTAS 2016 2

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SLIDE 6
  • Shift to COTS multicore

platforms

– Benefits: SWaP, performance/price ratio

  • Time-triggered (TT)

systems

– Used in many safety- critical domains like avionics

Motivation

April 12, 2016 WiP session RTAS 2016 2

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SLIDE 7
  • Shift to COTS multicore

platforms

– Benefits: SWaP, performance/price ratio

  • Time-triggered (TT)

systems

– Used in many safety- critical domains like avionics – Benefits: system-wide determinism, ease of certification, reduced costs etc.

Motivation

April 12, 2016 WiP session RTAS 2016 2

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SLIDE 8
  • Shift to COTS multicore

platforms

– Benefits: SWaP, performance/price ratio

  • Time-triggered (TT)

systems

– Used in many safety- critical domains like avionics – Benefits: system-wide determinism, ease of certification, reduced costs etc.

Combine benefits & Use in next-generation Integrated Modular Avionics (IMA)

T

Combine benefits & Use in next-generation Integrated Modular Avionics (IMA)

T

Motivation

April 12, 2016 WiP session RTAS 2016 2

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SLIDE 9

Problem & Challenges

April 12, 2016 WiP session RTAS 2016 3

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SLIDE 10

Problem & Challenges

April 12, 2016 WiP session RTAS 2016 3

Problem: Enable TT scheduling on COTS multicores

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SLIDE 11

Problem & Challenges

COTS Multicore Challenges

April 12, 2016 WiP session RTAS 2016 3

Problem: Enable TT scheduling on COTS multicores

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SLIDE 12

Problem & Challenges

COTS Multicore Challenges TT Challenges

April 12, 2016 WiP session RTAS 2016 3

Problem: Enable TT scheduling on COTS multicores

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SLIDE 13

Problem & Challenges

COTS Multicore Challenges

  • Shared hardware resources →

resource contentions

TT Challenges

April 12, 2016 WiP session RTAS 2016 3

Problem: Enable TT scheduling on COTS multicores

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SLIDE 14

Problem & Challenges

COTS Multicore Challenges

  • Shared hardware resources →

resource contentions

  • Naive soln.: Assume worst-

case contention → too pessimistic

TT Challenges

April 12, 2016 WiP session RTAS 2016 3

Problem: Enable TT scheduling on COTS multicores

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SLIDE 15

Problem & Challenges

COTS Multicore Challenges

  • Shared hardware resources →

resource contentions

  • Naive soln.: Assume worst-

case contention → too pessimistic

  • MemGuard (HRT version)

– No mention of task deadline and ET computation – Fixed memory server budget per core

TT Challenges

April 12, 2016 WiP session RTAS 2016 3

Problem: Enable TT scheduling on COTS multicores

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SLIDE 16

Problem & Challenges

COTS Multicore Challenges

  • Shared hardware resources →

resource contentions

  • Naive soln.: Assume worst-

case contention → too pessimistic

  • MemGuard (HRT version)

– No mention of task deadline and ET computation – Fixed memory server budget per core

TT Challenges

April 12, 2016 WiP session RTAS 2016 3

Problem: Enable TT scheduling on COTS multicores

  • For each task, guarantee
  • ffline:
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SLIDE 17

Problem & Challenges

COTS Multicore Challenges

  • Shared hardware resources →

resource contentions

  • Naive soln.: Assume worst-

case contention → too pessimistic

  • MemGuard (HRT version)

– No mention of task deadline and ET computation – Fixed memory server budget per core

TT Challenges

April 12, 2016 WiP session RTAS 2016 3

Problem: Enable TT scheduling on COTS multicores

  • For each task, guarantee
  • ffline:

– Maximum number of runtime inter-core interferences

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SLIDE 18

Problem & Challenges

COTS Multicore Challenges

  • Shared hardware resources →

resource contentions

  • Naive soln.: Assume worst-

case contention → too pessimistic

  • MemGuard (HRT version)

– No mention of task deadline and ET computation – Fixed memory server budget per core

TT Challenges

April 12, 2016 WiP session RTAS 2016 3

Problem: Enable TT scheduling on COTS multicores

  • For each task, guarantee
  • ffline:

– Maximum number of runtime inter-core interferences – latency of runtime inter core interferences

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SLIDE 19

Problem & Challenges

COTS Multicore Challenges

  • Shared hardware resources →

resource contentions

  • Naive soln.: Assume worst-

case contention → too pessimistic

  • MemGuard (HRT version)

– No mention of task deadline and ET computation – Fixed memory server budget per core

TT Challenges

April 12, 2016 WiP session RTAS 2016 3

Problem: Enable TT scheduling on COTS multicores

  • For each task, guarantee
  • ffline:

– Maximum number of runtime inter-core interferences – latency of runtime inter core interferences

  • Runtime mechanism that

upholds offline guarantees

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SLIDE 20

Problem & Challenges

COTS Multicore Challenges

  • Shared hardware resources →

resource contentions

  • Naive soln.: Assume worst-

case contention → too pessimistic

  • MemGuard (HRT version)

– No mention of task deadline and ET computation – Fixed memory server budget per core

TT Challenges

April 12, 2016 WiP session RTAS 2016 3

Problem: Enable TT scheduling on COTS multicores

  • For each task, guarantee
  • ffline:

– Maximum number of runtime inter-core interferences – latency of runtime inter core interferences

  • Runtime mechanism that

upholds offline guarantees

  • Find valid offline schedule
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SLIDE 21

System Model: Freescale QorIQ P4080

April 12, 2016 4 WiP session RTAS 2016

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SLIDE 22

System Model: Freescale QorIQ P4080

April 12, 2016 4 WiP session RTAS 2016

Source: Freescale P4080 Reference Manual, Rev. 3.

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SLIDE 23

System Model: Freescale QorIQ P4080

April 12, 2016 4 WiP session RTAS 2016

Source: Freescale P4080 Reference Manual, Rev. 3.

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SLIDE 24

System Model: Freescale QorIQ P4080

April 12, 2016 4 WiP session RTAS 2016

Source: Freescale P4080 Reference Manual, Rev. 3.

Processing Cores Processing Cores

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SLIDE 25

System Model: Freescale QorIQ P4080

April 12, 2016 4 WiP session RTAS 2016

Source: Freescale P4080 Reference Manual, Rev. 3.

Processing Cores Processing Cores On-chip Network On-chip Network

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SLIDE 26

System Model: Freescale QorIQ P4080

April 12, 2016 4 WiP session RTAS 2016

Source: Freescale P4080 Reference Manual, Rev. 3.

Processing Cores Processing Cores On-chip Network On-chip Network Memory Sub-system Memory Sub-system

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SLIDE 27

Proposed Method

April 12, 2016 WiP session RTAS 2016 5

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SLIDE 28

Proposed Method

  • Phase 1

April 12, 2016 WiP session RTAS 2016 5

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SLIDE 29

Proposed Method

  • Phase 1

– Runtime

April 12, 2016 WiP session RTAS 2016 5

slide-30
SLIDE 30

Proposed Method

  • Phase 1

– Runtime

April 12, 2016 WiP session RTAS 2016 5

1 3 2 5 4 6 Time t (ms) 7

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SLIDE 31

Proposed Method

  • Phase 1

– Runtime – N cores

April 12, 2016 WiP session RTAS 2016 5

1 3 2 5 4 6 Time t (ms) 7

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SLIDE 32

Proposed Method

  • Phase 1

– Runtime – N cores

April 12, 2016 WiP session RTAS 2016 5

1 3 2 5 4 6 Time t (ms) 7 Core 1 Core 2 Core 3

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SLIDE 33

Proposed Method

  • Phase 1

– Runtime – N cores – 2 servers per core

April 12, 2016 WiP session RTAS 2016 5

1 3 2 5 4 6 Time t (ms) 7 Core 1 Core 2 Core 3

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SLIDE 34

Proposed Method

  • Phase 1

– Runtime – N cores – 2 servers per core

April 12, 2016 WiP session RTAS 2016 5

1 3 2 5 4 6 Time t (ms) 7 Core 1 Core 2 Core 3 τsp1 τsp2 τsp3

S S S

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SLIDE 35

Proposed Method

  • Phase 1

– Runtime – N cores – 2 servers per core

April 12, 2016 WiP session RTAS 2016 5

1 3 2 5 4 6 Time t (ms) 7 Core 1 Core 2 Core 3 τsp1 τsp2 τsp3

S S S

τsm1 τsm2 τsm3

Acc1 Acc1 Acc2 Acc3 Acc2 Acc3 Acc1 Acc2 Acc3

slide-36
SLIDE 36

Proposed Method

  • Phase 1

– Runtime – N cores – 2 servers per core – Synchronous release of servers

April 12, 2016 WiP session RTAS 2016 5

1 3 2 5 4 6 Time t (ms) 7 Core 1 Core 2 Core 3 τsp1 τsp2 τsp3

S S S

τsm1 τsm2 τsm3

Acc1 Acc1 Acc2 Acc3 Acc2 Acc3 Acc1 Acc2 Acc3

slide-37
SLIDE 37

Proposed Method

  • Phase 1

– Runtime – N cores – 2 servers per core – Synchronous release of servers

April 12, 2016 WiP session RTAS 2016 5

1 3 2 5 4 6 Time t (ms) 7 Core 1 Core 2 Core 3 τsp1 τsp2 τsp3

S S S

τsm1 τsm2 τsm3

Acc1 Acc1 Acc2 Acc3 Acc2 Acc3 Acc1 Acc2 Acc3

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SLIDE 38

Proposed Method

  • Phase 1

– Runtime – N cores – 2 servers per core – Synchronous release of servers – Regulates contention & latency

April 12, 2016 WiP session RTAS 2016 5

1 3 2 5 4 6 Time t (ms) 7 Core 1 Core 2 Core 3 τsp1 τsp2 τsp3

S S S

τsm1 τsm2 τsm3

Acc1 Acc1 Acc2 Acc3 Acc2 Acc3 Acc1 Acc2 Acc3

slide-39
SLIDE 39

Proposed Method

  • Phase 1

– Runtime – N cores – 2 servers per core – Synchronous release of servers – Regulates contention & latency

  • Phase 2

April 12, 2016 WiP session RTAS 2016 5

1 3 2 5 4 6 Time t (ms) 7 Core 1 Core 2 Core 3 τsp1 τsp2 τsp3

S S S

τsm1 τsm2 τsm3

Acc1 Acc1 Acc2 Acc3 Acc2 Acc3 Acc1 Acc2 Acc3

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SLIDE 40

Proposed Method

  • Phase 1

– Runtime – N cores – 2 servers per core – Synchronous release of servers – Regulates contention & latency

  • Phase 2

– Offline

April 12, 2016 WiP session RTAS 2016 5

1 3 2 5 4 6 Time t (ms) 7 Core 1 Core 2 Core 3 τsp1 τsp2 τsp3

S S S

τsm1 τsm2 τsm3

Acc1 Acc1 Acc2 Acc3 Acc2 Acc3 Acc1 Acc2 Acc3

slide-41
SLIDE 41

Proposed Method

  • Phase 1

– Runtime – N cores – 2 servers per core – Synchronous release of servers – Regulates contention & latency

  • Phase 2

– Offline – TT Schedule

April 12, 2016 WiP session RTAS 2016 5

1 3 2 5 4 6 Time t (ms) 7 Core 1 Core 2 Core 3 τsp1 τsp2 τsp3

S S S

τsm1 τsm2 τsm3

Acc1 Acc1 Acc2 Acc3 Acc2 Acc3 Acc1 Acc2 Acc3

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SLIDE 42

τ1,1 τ1,1 τ1,1 τ1,1 τ2,1 τ2,1 τ2,2 τ2,3 τ2,3

Proposed Method

  • Phase 1

– Runtime – N cores – 2 servers per core – Synchronous release of servers – Regulates contention & latency

  • Phase 2

– Offline – TT Schedule

April 12, 2016 WiP session RTAS 2016 5

1 3 2 5 4 6 Time t (ms) 7 Core 1 Core 2 Core 3 τsp1 τsp2 τsp3

S S S

τsm1 τsm2 τsm3

Acc1 Acc1 Acc2 Acc3 Acc2 Acc3 Acc1 Acc2 Acc3

τ3,1 τ3,1 τ3,1 τ3,2 τ3,2 τ3,2

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SLIDE 43

Summary

April 12, 2016 6 WiP session RTAS 2016

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SLIDE 44

Summary

  • Accounts for contention in on-chip network as

well as memory sub-system

April 12, 2016 6 WiP session RTAS 2016

slide-45
SLIDE 45

Summary

  • Accounts for contention in on-chip network as

well as memory sub-system

  • Bounds variability in ET considering specified

constraints

April 12, 2016 6 WiP session RTAS 2016

slide-46
SLIDE 46

Summary

  • Accounts for contention in on-chip network as

well as memory sub-system

  • Bounds variability in ET considering specified

constraints

  • Prototype implemented bare-metal on real

COTS multicore - P4080

April 12, 2016 6 WiP session RTAS 2016

slide-47
SLIDE 47

Summary

  • Accounts for contention in on-chip network as

well as memory sub-system

  • Bounds variability in ET considering specified

constraints

  • Prototype implemented bare-metal on real

COTS multicore - P4080

  • Generic: can be used by other schedulers as

well

April 12, 2016 6 WiP session RTAS 2016

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SLIDE 48

Summary

  • Accounts for contention in on-chip network as

well as memory sub-system

  • Bounds variability in ET considering specified

constraints

  • Prototype implemented bare-metal on real

COTS multicore - P4080

  • Generic: can be used by other schedulers as

well

April 12, 2016 6 WiP session RTAS 2016

Initial step towards enabling TT scheduling on COTS multicores Initial step towards enabling TT scheduling on COTS multicores

slide-49
SLIDE 49

April 12, 2016 7 WiP session RTAS 2016

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SLIDE 50

Questions?

April 12, 2016 7 WiP session RTAS 2016

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SLIDE 51

Questions?

April 12, 2016 7 WiP session RTAS 2016

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SLIDE 52

Questions?

April 12, 2016 7 WiP session RTAS 2016

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SLIDE 53

Questions?

April 12, 2016 7 WiP session RTAS 2016

MET vs. WCET?

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SLIDE 54

Questions?

April 12, 2016 7 WiP session RTAS 2016

MET vs. WCET?

Visit us in the poster session!

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SLIDE 55

Questions?

April 12, 2016 7 WiP session RTAS 2016

MET vs. WCET?

Visit us in the poster session!

Thank You!