SiP Technology and Testing Name: Philippe Cauvet Date: 2007, March - - PowerPoint PPT Presentation

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SiP Technology and Testing Name: Philippe Cauvet Date: 2007, March - - PowerPoint PPT Presentation

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SiP Technology and Testing Name: Philippe Cauvet Date: 2007, March 28 Outline Definition Market / Applications Design and technology Packaging Technologies Test Challenges Conclusion 2 Journe EEA Montpellier Philippe

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SiP Technology and Testing

Name: Philippe Cauvet Date: 2007, March 28

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 2

  • Definition
  • Market / Applications
  • Design and technology
  • Packaging Technologies
  • Test Challenges
  • Conclusion

Outline

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SLIDE 3

Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 3

System-in-package (SiP) = any combination of semiconductors, passives, and interconnects integrated into a single package SiP (System-in-Package) is a functional system or subsystem assembled into a single package

What is a SiP?

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 4

  • Definition
  • Market / Applications
  • Design and technology
  • Packaging Technologies
  • Test Challenges
  • Conclusion

Outline

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 5

Market Trends

Industry moves to SiP

SiP Market Projection

2 000 4 000 6 000 8 000 10 000 12 000 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 Mu Shipment 2 000 4 000 6 000 8 000 10 000 12 000 Automotive Communications Consumer Data Processing Industrial Source: Gartner 1Q06

CAGR 04-10 10%

Gartner updates every quarter its SiP Market Projection

Gartner view slightly increased since 3Q04 with 10% CAGR 04-09 compared to 5% CAGR 04-09 for Semiconductors: SiP and SoC grow in parallel! Gartner sees as much SiP in Consumer as Communication Why a slowdown ? Missing CAD tools certainly an obstacle

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 6

Leading Applications for SiPs

  • Applications include portable consumer products such as

digital camcorders and cameras

  • Mobile phone is the volume driver

– Logic and memory combo – Digital baseband section – Transceiver section – RF section

Applications

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 7

SiPs show up in portable devices

Applications: DSC

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 8

Applications: Mobile phones

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 9

Applications: BluetoothTM

Bluetooth Radio: >1Billion Units shipped in 2006

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 10

Applications: OneChipSTB

Tuner MPEG2

Video & Audio

Decoder Channel Tuner MPEG2

Video & Audio

Decoder Channel

(drawing not to scale)

BGA292 Pics die 268 wires 64.4 mm²

9.43 mm 6.83 mm

MOJO die PNX8316 292 bumps 20.4mm² - 1W

Channel die TDA10086 72 bumps 7.4mm² - 0.76W

Tuner die TDA8262 50 bumps 4.9mm² - 0.58W

MPEG2 A/V decoder Channel decoder Silicon Tuner

(drawing not to scale)

BGA292 Pics die 268 wires 64.4 mm²

9.43 mm 6.83 mm

MOJO die PNX8316 292 bumps 20.4mm² - 1W

Channel die TDA10086 72 bumps 7.4mm² - 0.76W

Tuner die TDA8262 50 bumps 4.9mm² - 0.58W

(drawing not to scale)

BGA292 Pics die 268 wires 64.4 mm²

9.43 mm 6.83 mm

MOJO die PNX8316 292 bumps 20.4mm² - 1W

Channel die TDA10086 72 bumps 7.4mm² - 0.76W

Tuner die TDA8262 50 bumps 4.9mm² - 0.58W

MPEG2 A/V decoder Channel decoder Silicon Tuner MPEG2 A/V decoder Channel decoder Silicon Tuner MPEG2 A/V decoder Channel decoder Silicon Tuner

One board PCB 2 layers

Smart Card(s) 16Mb SDRAM Audio DAC EEPROM 16Kb 4Mb FLASH UARTs

16 CINCH Right CINCH Left Analogue video SVHS CVBS RF input ISO7816 16 I²C

One package STB sbSIP + technology

I²S

Front panel Bi-colour LED and IrDA Receiver

One board PCB 2 layers

Smart Card(s) 16Mb SDRAM Audio DAC EEPROM 16Kb 4Mb FLASH UARTs

16 CINCH Right CINCH Left Analogue video SVHS CVBS RF input ISO7816 16 I²C

One package STB sbSIP + technology

I²S

Front panel Bi-colour LED and IrDA Receiver

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 11

  • Definition
  • Market / Applications
  • Design and technology
  • Packaging Technologies
  • Test Challenges
  • Conclusion

Outline

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 12

SiP vs SoC (1)

Single piece of silicon Single technology Single level of interconnection Multiple chips Multiple technologies Multiple levels of interconnection… …and 3D

SoC SiP

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 13

Technical Mix Performance / Speed Production Volume Time to Market

Short Long Low High Low High Complex Simple

Favor the use

  • f SoC.

Favor the use

  • f SiP.

Consider Factors Carefully. Consider Factors Carefully.

Factors to Consider: Production Volume Design Environment Dev Cost (Incl. IP Cost) Reliability Die Maturity Technologies (RF, Memories…)

+ Market Environment

Source: Gartner 2006 Contibutor: JM Yannou, NXP SiP Innovation Manager

SiP vs SoC (2)

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 14

Focus on EMC (and SiP): new challenges

non SiP system SiP

? ?

system goes 3D! + components are closer to each other! Components placement is done empirically after circuits design Components placement is done at the same time as circuits design: predictability needed!

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 15

Example of an inter-system (inter SiP in susceptibility) EMC challenge

The GSM antenna emits signals considered as noise by the close-by low-amplitude large-bandwidth TV RF receiving subsystem

TV: up to 862MHz GSM: from 890MHz on TV: up to 862MHz GSM: from 890MHz on

Decoupling capacitors integrated in silicon (Philips PICS technology), flip-chip bumped on digital: -16dB noise reduction measured! Digital IC Analog IC

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 16

  • Definition
  • Market / Applications
  • Design and technology
  • Packaging Technologies
  • Test Challenges
  • Conclusion

Outline

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 17

SiP vs SoC

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 18

Packaging challenges

  • Higher integration requires smaller chips, with smaller pad

pitch and size

  • More chips = thinner chips (how to handle <100µm

wafers?)

  • More functionalities = more power
  • Cost of materials
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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 19

Packaging

Source: STATSChippac

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 20

Packaging

Source: DPC

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 21 15

Intel

Package-on-Package construction (folded flex circuit from Tessera)

– Processor, flash & SDRAM

Prototype of 8-dies stack with no interposer (50µm die thickness) Intel is now using copper pillar bumping for its processors

Packaging

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 22

Tessera

Package-on-Package (folded carrier)

– 2 metal-layer polymide providing electrical and mechanical properties for interconnect

Processor with associated memory

Carrier R L (Q) C Interconnectivity

Flex no 60 no 14 lines/mm Si/GaAs no ? 0,11nF/mm² ?

Sources : Prismark wireless technology report – March 2005 Folded Stacked CSP assembly process Tessera/Intel folded stacked CSP package Configuration examples

Packaging

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 23

MMM6000 Module

Freescale

Single package transceiver for quad band EGPRS (GSM/GPRS/EDGE)

– 11.2x9mm – 9 SMDs 0402 – 18 SMDs 0201 – 2.8x2.6mm 0.13µm CMOS – 2.7x2.9mm 0.18µm RFCMOS – 1.1x1.1mm IPD device

Packaging

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 24

Sychip

? Known Partnerships Sampling? Availability 12x12 I/O 9x9 Size (mm)

Silicon substrate with integrated passives

Source : Sychip

Packaging

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 25

Key benefits

  • Performance (flip chip interconnects)

Inductance / 4 to 6!

  • Size (3D stacking, passive integration)
  • Low thermal resistance

NXP Silicon-based SiP concept

lead tip lead tip Active die

Passive die

Molding compound

Flip chip Active die Flip chip Passive die Standard HVQFN package

Packaging

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 26

MEMS Packaging

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 27

MEMS packaging SAW filter on silicon substrate

LiTaO3 LiTaO3

Assembly enabling an electrical contact and sealing Assembly: Thermo-compression Polymer pattern on PICS PICS substrate LiTaO3 substrate SAW filter Cavity Assembly enabling an electrical contact and sealing Assembly enabling an electrical contact and sealing Assembly: Thermo-compression Assembly: Thermo-compression Polymer pattern on PICS PICS substrate LiTaO3 substrate SAW filter Cavity Polymer pattern on PICS PICS substrate LiTaO3 substrate SAW filter Cavity

PICS substrate SAW filter Gold stud-bump Polymer seal ring

1mm 1mm

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 28 26

MEMS Acceloremeter stacked die package

STMicroelectronics

Targeted applications

– Toys, medicals, phones, anti-theft

4.3x4.0x0.4mm MEMS die 3.9x4.0x0.4mm cap die 3x2.8x0.2mm logic die QFN 28 I/O, 2 stacked die Die to die and die-leadframe wirebonds

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 29

  • Definition
  • Market / Applications
  • Design and technology
  • Packaging Technologies
  • Test Challenges
  • Conclusion

Outline

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 30

Circuit Functions Process Techno. Suppliers Quality Levels Supply Voltages Signal Frequencies Signal Levels Failure mod./mech.

SiP vs SoC

Compared to a Compared to a SoC SoC, a , a SiP SiP may have more may have more… …

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 31

Chip A Chip B Chip C

Today:

+ Test of PCB + Interconnects + Passives + Functional

Test Test Test

Test cost = 3U Test cost = 4U

Future (w SiP):

  • Test of PCB
  • Interconnects
  • Passives (almost 0!)

= Functional Test cost < 3U Test cost << 4U With a Higher Coverage!

NXP SiP Test Vision

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 32

System-level Test:

  • Quality level
  • Yield

at a reasonable

  • Test cost!

Fab of X & PCM Test Fab of B Fab of A & PCM Test SiP Packaging. Die X Wafer Test Die B Die A Wafer Test SiP Final Test

D E L I V E R Y

Fab of X & PCM Test Fab of B Fab of A & PCM Test SiP Packaging. Die X Wafer Test Die B Die A Wafer Test Die X Wafer Test Die B Die A Wafer Test SiP Final Test

D E L I V E R Y

A Complex Test Flow…

System-level Test:

  • DfT
  • Fast Diagnosis

and…

  • Known-Good-Dies!

Passive Substrate

Analog/RF

Digital or Mixed-mode

Wafer Test Final Test

Known Good Dies!

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 33

KGD Definition:

(from a test perspective)

  • Good enough to meet, at die level, at least the same

quality level as a packaged IC

  • Implies that :
  • KGD test = WT + FT of a packaged die!!

Known-Good-Die

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 34

Cantilever RF probing concept

Bonding: 1-3mm Leadframe: mm size

Package: Wire bonding length

Probe tips: 3-5mm Total Probe length: 10-15mm

Die under probes: Needle length

Rule of thumb: 10mm represent 10nH serial inductance impossible to test a PA @freq, for example!

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 35

Thin film technologies for RF probing

Contact bumps Membrane Microstrip transmission line Ground plane

Carrier PCB Membrane Forced-delivery mechanism Contact bumps Terminations and bypasses Carrier PCB Membrane Forced-delivery mechanism Contact bumps Terminations and bypasses

40um-60um

Thin film, Μ r 25um

40um-60um

Thin film, Μ r 25um

40um-60um

Thin film, Μ r 25um

Rule of thumb: 0.05mm represents less than 0.5nH serial inductance (typical 0.2nH specified)

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 36

  • Springs for solder

bumps

  • Cantilevers for

contact pads

  • RMS roughness 15

nm

  • Length to 600 µm
  • Width 29-55 µm
  • Thickness 11 µm
  • Planarity 1.07 µm
  • ver 1 mm range

MEMS technologies for RF probing

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 37

Full Test at Wafer

Alternative Test Methods

IDD R

L = 1 n H CLKI N VOS C CLKOU T (Reference Clock Signal) Package

CLPF RLP

F

(VDD Test Pattern)

DUT

VCLK

  • Power supply sweep
  • I-V Signatures
  • Multiple observation points
  • Simple method
  • “black-box” methodology
  • No functional testing
  • Short test time

Signature-based Testing

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 38

Management of diversity

Which leads SiP package test to: Require greater diversity of ATE resources than SoC Require greater diversity of test & reliability screen methods than SoC Have large disparities in test times and resource utilization among die Solutions: Insert in multiple testers Better scheduling of test resources to allow independent, simultaneous test

  • f each accessible chip in SiP

BIST / DfT / DSP

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 39

So, what to do?

Philips: DigRF interface advantage vs disadvantage Philips: DigRF interface advantage vs disadvantage

Data bits

TX RX

D A D A LNA PA AGC Buf DSP core

TX-FEM Transceiver Baseband

Intermediate Test Points may affect signal integrity and leads to longer test times

System Testing Issues

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 40

Philips: DigRF interface advantage vs disadvantage Philips: DigRF interface advantage vs disadvantage

Data bits

TX RX

D A D A LNA PA AGC Buf DSP core

TX-FEM Transceiver Baseband

1. Test Rx and Tx paths independently

Ref: “Seamless test of Digital Components in M/S paths”, S. Ozev et al

Pro: Pro:

  • close to the application conditions
  • two-pass test = reduced test time
  • reduced risk of signal degradation

DSP DSP

Modulated RF Modulated RF Contra: Contra:

  • expensive ATE
  • quality of contacts critical
  • diagnosis??
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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 41

Philips: DigRF interface advantage vs disadvantage Philips: DigRF interface advantage vs disadvantage

Data bits

TX RX

D A D A LNA PA AGC Buf DSP core

TX-FEM Transceiver Baseband

  • 2. Test Rx and Tx paths together (loop-back)

Ref: “Wafer level RF Test and DfT for VCO Modulating Transceiver Architectures”, S. Ozev et al

Pro: Pro:

  • low-cost (no?) ATE
  • benefit from PICS capabilities
  • test simulation
  • easier BIST implementation

DSP DSP

Contra: Contra:

  • need DfT (not a simple short-circuit!)
  • correlation with lab measurements
  • mgt of yield / test escapes
  • diagnosis??
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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 42

LO

ADC1 DAC1

HPA LNA

BPF BPF BPF VGA ADC N ADC M

Mixed Signal Die Transceiver : RF Die Auxiliary function Auxiliary function

LO

ADC1 DAC1

HPA LNA

BPF BPF BPF VGA ADC N ADC M

Mixed Signal Die Transceiver : RF Die Auxiliary function Auxiliary function

Biggest advantage:

Full digital test

Challenges:

Loop-back: Analog Design For Test issue

Test methods: digital post processing

ADCs DACs test Compensate data converters errors improve their performances

similar to measurement instruments

Test each block through other blocks

Loop-back starts at the beginning

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 43

Loop-back starts at the beginning

Strategy:

1. Find DSP-based methods / algorithms to re-use the analog/ms blocks as instruments 2. Implement hardware that supports the methods

DAC3 ADC4 DAC1 DAC4 ADC3 ADC1 ADC2 RF Part Digital part 2 Analog Part 1 Analog Part 2 Analog Part 1 Digital part 3 Digital part 4 Digital part 1

ANC

DAC3 ADC4 DAC1 DAC4 ADC3 ADC1 ADC1 ADC2 RF Part Digital part 2 Analog Part 1 Analog Part 2 Analog Part 1 Digital part 3 Digital part 4 Digital part 1

ANC ANC

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 44

Philips: DigRF interface advantage vs disadvantage Philips: DigRF interface advantage vs disadvantage

Data

TX RX

D A D A LNA PA AGC Buf DSP core

TX-FEM Transceiver Baseband

SiP Testing

  • Diagnosis capabilities using signatures

DSP DSP

Faults Faults Faults

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 45

Testing Wirelessly (LIRMM+NXP)

Transmitter/ Receiver

ATE

SIP

Test Control Block

Die 1 Die 2 Die 3

Architecture for testing a SiP wirelessly

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 46

  • Definition
  • Market / Applications
  • Design and technology
  • Packaging Technologies
  • Test Challenges
  • Conclusion

Outline

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 47

Summary

  • SiP is:
  • significantly growing
  • not a SoC
  • represents many challenges in:
  • design (tools, EMC,…)
  • packaging (stacked, planar, PiP, PoP, …)
  • test (KGD, System Testing,…)

thus, SiP technologies offer many perspectives /

  • pportunities

to students, researchers and engineers

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Thank You

philippe.cauvet@nxp.com

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 50

Le Mastère Spécialisé « Microelectronics System Design & Technology » forme des spécialistes de la conception de systèmes micro-électroniques & micro-technologiques The specialized Master in « Microelectronics System Design & Technology » trains specialists in micro-electronic and micro- technological systems design

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Philippe Cauvet, Mar 28, 2007

Journée EEA Montpellier 51

Advanced Processes 60h Coupling Effects 60h Advanced Tests 80h SiP Design Methodologies 80h Manufacturing 40h Business Management 40h SoC Design Methodologies 60h Introduction 20h

Executive Master’s Degree (Bac+6)

1470 hours

  • 560 h classrooms (5 months) and
  • exercises (1 month)
  • 910 h Internship (6 months)

2 intakes: February and September CONTACTS pierre.vancaenegen@ensicaen.fr christophe.goupil@ensicaen.fr nathalie.carpentier@nxp.com