Silver Sintering for Power Electronics Integration Cyril B UTTAY , - PowerPoint PPT Presentation

Silver Sintering for Power Electronics Integration Cyril B UTTAY , Bruno A LLARD , Raphaël R IVA Laboratoire Ampère, Lyon, France 17/4/15 1 / 25

Outline Introduction Integration of gate driver circuit Double-side Cooling Conclusion 2 / 25

Outline Introduction Integration of gate driver circuit Double-side Cooling Conclusion 3 / 25

Active Power Devices for High Temperature Falahi et Al. “High temperature, Smart Power Module for aircraft actuators”, HiTEN 2013 250 -50 ◦ C -10 ◦ C 27 ◦ C 70 ◦ C 107 ◦ C 70 310°C 200 60 160 ◦ C 150 50 Drain current [A] 196 ◦ C V out [V] 40 100 234 ◦ C 270 ◦ C 30 50 20 0 10 50 0 49.0 48.8 48.6 48.4 0.2 0.0 0.2 0 2 4 6 8 10 12 time [ µ s] time [ µ s] Drain-to-Source voltage [V] Previous results show that SiC JFETs are attractive for > 200 ° C operation: ◮ rated at 1200 V (or more), several Amps ◮ Voltage-controlled devices ◮ No reliability issue related to gate oxide degradation 4 / 25

Gate Drivers for SiC JFETs 120 100 Drain Current [A] 80 ◮ Normally-on devices 60 ◮ negative blocking Vgs = 0.0 V voltage Vgs = 5.0 V 40 Vgs = 10.0 V ◮ threshold ≈ 20 V. Vgs = 15.0 V 20 Vgs = 20.0 V Vgs = 25.0 V 0 0 5 10 15 20 Drain-to-Source Voltage [V] ◮ Custom-designed gate driver ◮ SOI technology for high temperature capability. 5 / 25

Bonding Material: Silver Sintering Silver Paste ◮ Based on micro-scale silver particles (Heraeus LTS-117O2P2) ◮ Low temperature (240 ° C) sintering Göbl, C. et al “Low temperature sinter technology Die attachment for automotive ◮ Low pressure (2 MPa) process power electronic applications” proc of APE, 2006 No liquid phase involved: ◮ No movement of the die ◮ No bridging across terminals ◮ No height compensation thanks to wetting 6 / 25

Outline Introduction Integration of gate driver circuit Double-side Cooling Conclusion 7 / 25

What’s Inside and What’s Not? High-side gate driver V bus Dead-time Buffer Level-shifter Dead-time Buffer OUT Low-side gate driver Dead-time Buffer Level-shifter Dead-time Buffer GND 8 / 25

What’s Inside and What’s Not? High-side gate driver DC V bus DC Dead-time Buffer DC DC Level-shifter Dead-time Buffer DC OUT DC PWM generator Low-side gate driver DC DC Dead-time Buffer DC DC Level-shifter Dead-time Buffer DC DC GND ◮ Isolation functions (signal and power) ◮ PWM signal generation ◮ Large value decoupling capacitor (1 µ F ) 8 / 25

Pictures of the power module ◮ CuMo leadframe / NiFe frame case ◮ ceramic substrate (AlN) ≈ 20 × 30 mm 2 ◮ high temperature passives (Vishay, Presidio) ◮ Al wedge Wirebonds, except Au ball for driver ◮ Bonding: silver sintering 9 / 25

The Test Setup No encapsulation used ➜ V DC limited to 200 V Power module attached to a hotplate ➜ test from ambient to 315° C External components at room temp. ➜ signal and power isolation ➜ large DC capacitor Continuous operation on resistor 10 / 25

Measurements 250 200°C 200 V bus 150 V out [V] J H 100 50 OUT 0 50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] J L 5 GND 200°C 4 3 ◮ V DC = 200 V (no I out [A] 2 encapsulation) 1 ◮ R load = 50 Ω 0 ◮ F switch = 10 kHz 1 ◮ t dead − time = 1 . 2 µ s 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 11 / 25

Measurements 250 210°C 200 V bus 150 V out [V] J H 100 50 OUT 0 50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] J L 5 GND 210°C 4 3 ◮ V DC = 200 V (no I out [A] 2 encapsulation) 1 ◮ R load = 50 Ω 0 ◮ F switch = 10 kHz 1 ◮ t dead − time = 1 . 2 µ s 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 11 / 25

Measurements 250 220°C 200 V bus 150 V out [V] J H 100 50 OUT 0 50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] J L 5 GND 220°C 4 3 ◮ V DC = 200 V (no I out [A] 2 encapsulation) 1 ◮ R load = 50 Ω 0 ◮ F switch = 10 kHz 1 ◮ t dead − time = 1 . 2 µ s 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 11 / 25

Measurements 250 230°C 200 V bus 150 V out [V] J H 100 50 OUT 0 50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] J L 5 GND 230°C 4 3 ◮ V DC = 200 V (no I out [A] 2 encapsulation) 1 ◮ R load = 50 Ω 0 ◮ F switch = 10 kHz 1 ◮ t dead − time = 1 . 2 µ s 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 11 / 25

Measurements 250 240°C 200 V bus 150 V out [V] J H 100 50 OUT 0 50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] J L 5 GND 240°C 4 3 ◮ V DC = 200 V (no I out [A] 2 encapsulation) 1 ◮ R load = 50 Ω 0 ◮ F switch = 10 kHz 1 ◮ t dead − time = 1 . 2 µ s 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 11 / 25

Measurements 250 250°C 200 V bus 150 V out [V] J H 100 50 OUT 0 50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] J L 5 GND 250°C 4 3 ◮ V DC = 200 V (no I out [A] 2 encapsulation) 1 ◮ R load = 50 Ω 0 ◮ F switch = 10 kHz 1 ◮ t dead − time = 1 . 2 µ s 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 11 / 25

Measurements 250 260°C 200 V bus 150 V out [V] J H 100 50 OUT 0 50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] J L 5 GND 260°C 4 3 ◮ V DC = 200 V (no I out [A] 2 encapsulation) 1 ◮ R load = 50 Ω 0 ◮ F switch = 10 kHz 1 ◮ t dead − time = 1 . 2 µ s 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 11 / 25

Measurements 250 270°C 200 V bus 150 V out [V] J H 100 50 OUT 0 50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] J L 5 GND 270°C 4 3 ◮ V DC = 200 V (no I out [A] 2 encapsulation) 1 ◮ R load = 50 Ω 0 ◮ F switch = 10 kHz 1 ◮ t dead − time = 1 . 2 µ s 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 11 / 25

Measurements 250 280°C 200 V bus 150 V out [V] J H 100 50 OUT 0 50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] J L 5 GND 280°C 4 3 ◮ V DC = 200 V (no I out [A] 2 encapsulation) 1 ◮ R load = 50 Ω 0 ◮ F switch = 10 kHz 1 ◮ t dead − time = 1 . 2 µ s 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 11 / 25

Measurements 250 290°C 200 V bus 150 V out [V] J H 100 50 OUT 0 50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] J L 5 GND 290°C 4 3 ◮ V DC = 200 V (no I out [A] 2 encapsulation) 1 ◮ R load = 50 Ω 0 ◮ F switch = 10 kHz 1 ◮ t dead − time = 1 . 2 µ s 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 11 / 25

Measurements 250 300°C 200 V bus 150 V out [V] J H 100 50 OUT 0 50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] J L 5 GND 300°C 4 3 ◮ V DC = 200 V (no I out [A] 2 encapsulation) 1 ◮ R load = 50 Ω 0 ◮ F switch = 10 kHz 1 ◮ t dead − time = 1 . 2 µ s 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 11 / 25

Measurements 250 310°C 200 V bus 150 V out [V] J H 100 50 OUT 0 50 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] J L 5 GND 310°C 4 3 ◮ V DC = 200 V (no I out [A] 2 encapsulation) 1 ◮ R load = 50 Ω 0 ◮ F switch = 10 kHz 1 ◮ t dead − time = 1 . 2 µ s 49.0 48.8 48.6 48.4 0.2 0.0 0.2 time [ µ s] time [ µ s] 11 / 25

Outline Introduction Integration of gate driver circuit Double-side Cooling Conclusion 12 / 25

Double Side Cooling ◮ Standard packaging offers cooling through one side of the die only ◮ “3-D” or “Sandwich” package performs thermal management on both sides ◮ Requires suitable topside metal on the die ◮ Requires special features for topside contact 13 / 25

Double Side Cooling ◮ Standard packaging offers cooling through one side of the die only ◮ “3-D” or “Sandwich” package performs thermal management on both sides ◮ Requires suitable topside metal on the die ◮ Requires special features for topside contact 13 / 25

The proposed 3-D Structure V bus J H OUT J L GND ◮ Two ceramic substrates, in “sandwich” configuration ◮ Two SiC JFET dies (SiCED) ◮ assembled using silver sintering ◮ 25.4 mm × 12.7 mm (1 in × 0.5 in) 14 / 25

Ceramic Substrates Copper Alumina ◮ Si 3 N 4 identified previously for 0.16 mm high temperature 0.15 mm 0,15 mm Source Gate Source 0,3 mm ◮ For development: use of 0.2 mm alumina SiC JFET ◮ Etching accuracy exceeds 0.3 mm Drain standard design rules ◮ Double-step copper etching for die contact ➜ Custom etching technique Scale drawing for 2.4 × 2.4 mm 2 die 15 / 25

Preparation of the Substrates plain DBC board 16 / 25

Preparation of the Substrates plain DBC board 1a - Photosensitive resin coating 16 / 25

Preparation of the Substrates plain DBC board 1a - Photosensitive resin 1b - Exposure and coating Development 16 / 25

Preparation of the Substrates plain DBC board 1a - Photosensitive resin 1b - Exposure and 2 - Etching coating Development 16 / 25

Preparation of the Substrates plain DBC board 1a - Photosensitive resin 1b - Exposure and 2 - Etching coating Development 16 / 25