Silver Sintering for Power Electronics Integration Cyril B UTTAY , - - PowerPoint PPT Presentation

Silver Sintering for Power Electronics Integration

Cyril BUTTAY, Bruno ALLARD, Raphaël RIVA

Laboratoire Ampère, Lyon, France

17/4/15

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Outline Introduction Integration of gate driver circuit Double-side Cooling Conclusion

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Outline Introduction Integration of gate driver circuit Double-side Cooling Conclusion

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Active Power Devices for High Temperature

Falahi et Al. “High temperature, Smart Power Module for aircraft actuators”, HiTEN 2013

2 4 6 8 10 12 Drain-to-Source voltage [V] 10 20 30 40 50 60 70 Drain current [A]

• 50◦C -10◦C 27◦C

70◦C 107◦C 160◦C 196◦C 234◦C 270◦C 49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

310°C

Previous results show that SiC JFETs are attractive for > 200 ° C operation:

◮ rated at 1200 V (or more), several Amps ◮ Voltage-controlled devices ◮ No reliability issue related to gate oxide degradation

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Gate Drivers for SiC JFETs

5 10 15 20 Drain-to-Source Voltage [V] 20 40 60 80 100 120 Drain Current [A]

Vgs = 0.0 V Vgs = 5.0 V Vgs = 10.0 V Vgs = 15.0 V Vgs = 20.0 V Vgs = 25.0 V

◮ Normally-on devices ◮ negative blocking

voltage

◮ threshold ≈ 20 V. ◮ Custom-designed gate driver ◮ SOI technology for high temperature capability.

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Bonding Material: Silver Sintering

Göbl, C. et al “Low temperature sinter technology Die attachment for automotive power electronic applications” proc of APE, 2006

Silver Paste

◮ Based on micro-scale silver

particles (Heraeus LTS-117O2P2)

◮ Low temperature (240 °

C) sintering

◮ Low pressure (2 MPa) process

No liquid phase involved:

◮ No movement of the die ◮ No bridging across terminals ◮ No height compensation thanks to

wetting

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Outline Introduction Integration of gate driver circuit Double-side Cooling Conclusion

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What’s Inside and What’s Not?

Dead-time Dead-time Level-shifter Buffer Buffer Dead-time Dead-time Level-shifter Buffer Buffer

Vbus OUT GND High-side gate driver Low-side gate driver

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What’s Inside and What’s Not?

Dead-time Dead-time Level-shifter Buffer Buffer Dead-time Dead-time Level-shifter Buffer Buffer

Vbus OUT GND High-side gate driver Low-side gate driver DC DC DC DC DC DC DC DC DC DC DC DC PWM generator

◮ Isolation functions (signal and power) ◮ PWM signal generation ◮ Large value decoupling capacitor (1 µF)

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Pictures of the power module

◮ CuMo leadframe / NiFe frame case ◮ ceramic substrate (AlN) ≈ 20 × 30 mm2 ◮ high temperature passives (Vishay, Presidio) ◮ Al wedge Wirebonds, except Au ball for driver ◮ Bonding: silver sintering

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The Test Setup

No encapsulation used ➜ VDC limited to 200 V Power module attached to a hotplate ➜ test from ambient to 315° C External components at room temp. ➜ signal and power isolation ➜ large DC capacitor Continuous operation on resistor

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Measurements

49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

200°C

49.0 48.8 48.6 48.4 time [µs] 1 1 2 3 4 5 Iout [A] 0.2 0.0 0.2 time [µs]

200°C

Vbus OUT GND JH JL

◮ VDC = 200 V (no

encapsulation)

◮ Rload = 50 Ω ◮ Fswitch = 10 kHz ◮ tdead−time = 1.2 µs

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Measurements

49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

210°C

49.0 48.8 48.6 48.4 time [µs] 1 1 2 3 4 5 Iout [A] 0.2 0.0 0.2 time [µs]

210°C

Vbus OUT GND JH JL

◮ VDC = 200 V (no

encapsulation)

◮ Rload = 50 Ω ◮ Fswitch = 10 kHz ◮ tdead−time = 1.2 µs

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Measurements

49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

220°C

49.0 48.8 48.6 48.4 time [µs] 1 1 2 3 4 5 Iout [A] 0.2 0.0 0.2 time [µs]

220°C

Vbus OUT GND JH JL

◮ VDC = 200 V (no

encapsulation)

◮ Rload = 50 Ω ◮ Fswitch = 10 kHz ◮ tdead−time = 1.2 µs

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Measurements

49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

230°C

49.0 48.8 48.6 48.4 time [µs] 1 1 2 3 4 5 Iout [A] 0.2 0.0 0.2 time [µs]

230°C

Vbus OUT GND JH JL

◮ VDC = 200 V (no

encapsulation)

◮ Rload = 50 Ω ◮ Fswitch = 10 kHz ◮ tdead−time = 1.2 µs

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Measurements

49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

240°C

49.0 48.8 48.6 48.4 time [µs] 1 1 2 3 4 5 Iout [A] 0.2 0.0 0.2 time [µs]

240°C

Vbus OUT GND JH JL

◮ VDC = 200 V (no

encapsulation)

◮ Rload = 50 Ω ◮ Fswitch = 10 kHz ◮ tdead−time = 1.2 µs

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Measurements

49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

250°C

49.0 48.8 48.6 48.4 time [µs] 1 1 2 3 4 5 Iout [A] 0.2 0.0 0.2 time [µs]

250°C

Vbus OUT GND JH JL

◮ VDC = 200 V (no

encapsulation)

◮ Rload = 50 Ω ◮ Fswitch = 10 kHz ◮ tdead−time = 1.2 µs

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Measurements

49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

260°C

49.0 48.8 48.6 48.4 time [µs] 1 1 2 3 4 5 Iout [A] 0.2 0.0 0.2 time [µs]

260°C

Vbus OUT GND JH JL

◮ VDC = 200 V (no

encapsulation)

◮ Rload = 50 Ω ◮ Fswitch = 10 kHz ◮ tdead−time = 1.2 µs

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Measurements

49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

270°C

49.0 48.8 48.6 48.4 time [µs] 1 1 2 3 4 5 Iout [A] 0.2 0.0 0.2 time [µs]

270°C

Vbus OUT GND JH JL

◮ VDC = 200 V (no

encapsulation)

◮ Rload = 50 Ω ◮ Fswitch = 10 kHz ◮ tdead−time = 1.2 µs

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Measurements

49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

280°C

49.0 48.8 48.6 48.4 time [µs] 1 1 2 3 4 5 Iout [A] 0.2 0.0 0.2 time [µs]

280°C

Vbus OUT GND JH JL

◮ VDC = 200 V (no

encapsulation)

◮ Rload = 50 Ω ◮ Fswitch = 10 kHz ◮ tdead−time = 1.2 µs

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Measurements

49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

290°C

49.0 48.8 48.6 48.4 time [µs] 1 1 2 3 4 5 Iout [A] 0.2 0.0 0.2 time [µs]

290°C

Vbus OUT GND JH JL

◮ VDC = 200 V (no

encapsulation)

◮ Rload = 50 Ω ◮ Fswitch = 10 kHz ◮ tdead−time = 1.2 µs

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Measurements

49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

300°C

49.0 48.8 48.6 48.4 time [µs] 1 1 2 3 4 5 Iout [A] 0.2 0.0 0.2 time [µs]

300°C

Vbus OUT GND JH JL

◮ VDC = 200 V (no

encapsulation)

◮ Rload = 50 Ω ◮ Fswitch = 10 kHz ◮ tdead−time = 1.2 µs

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Measurements

49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

310°C

49.0 48.8 48.6 48.4 time [µs] 1 1 2 3 4 5 Iout [A] 0.2 0.0 0.2 time [µs]

310°C

Vbus OUT GND JH JL

◮ VDC = 200 V (no

encapsulation)

◮ Rload = 50 Ω ◮ Fswitch = 10 kHz ◮ tdead−time = 1.2 µs

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Outline Introduction Integration of gate driver circuit Double-side Cooling Conclusion

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Double Side Cooling

◮ Standard packaging offers cooling through one side of the

die only

◮ “3-D” or “Sandwich” package performs thermal

management on both sides

◮ Requires suitable topside metal on the die ◮ Requires special features for topside contact

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Double Side Cooling

◮ Standard packaging offers cooling through one side of the

die only

◮ “3-D” or “Sandwich” package performs thermal

management on both sides

◮ Requires suitable topside metal on the die ◮ Requires special features for topside contact

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The proposed 3-D Structure

Vbus OUT GND JH JL

◮ Two ceramic substrates, in “sandwich” configuration ◮ Two SiC JFET dies (SiCED) ◮ assembled using silver sintering ◮ 25.4 mm×12.7 mm (1 in×0.5 in)

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Ceramic Substrates

SiC JFET Alumina

0.2 mm

0,3 mm

0.16 mm

0,15 mm

Copper

0.15 mm

Gate Source Source Drain

0.3 mm

Scale drawing for 2.4×2.4 mm2 die

◮ Si3N4 identified previously for

high temperature

◮ For development: use of

alumina

◮ Etching accuracy exceeds

standard design rules

◮ Double-step copper etching for

die contact ➜ Custom etching technique

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Preparation of the Substrates

plain DBC board

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Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating

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Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development

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Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching

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Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching

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Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching 3a - resin coating

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Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching 3a - resin coating 3b - Exposure and Developpment

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Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching 3a - resin coating 3b - Exposure and Developpment 4a - Photosentive film laminating

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Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching 3a - resin coating 3b - Exposure and Developpment 4a - Photosentive film laminating 4b - Exposure and Development

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Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching 3a - resin coating 3b - Exposure and Developpment 4a - Photosentive film laminating 4b - Exposure and Development 5 - Etching

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Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching 3a - resin coating 3b - Exposure and Developpment 4a - Photosentive film laminating 4b - Exposure and Development 5 - Etching

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Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching 3a - resin coating 3b - Exposure and Developpment 4a - Photosentive film laminating 4b - Exposure and Development 5 - Etching 6 - Singulating

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Preparation of the Substrates

◮ Final patterns within 50 µm of desired size ◮ Two designs, for 2.4×2.4 mm2 and 4×4 mm2 dies ◮ Total copper thickness 300 µm, ≈ 150 µm per step

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Preparation of the Dies

◮ Standard aluminium topside finish

not compatible with silver sintering

◮ Ti/Ag PVD on contact areas ◮ Need for a masking solution

➜ jig with locating pockets.

Die Mask PVD

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Preparation of the Dies

◮ Standard aluminium topside finish

not compatible with silver sintering

◮ Ti/Ag PVD on contact areas ◮ Need for a masking solution

➜ jig with locating pockets.

Die Mask PVD

Before PVD

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Preparation of the Dies

◮ Standard aluminium topside finish

not compatible with silver sintering

◮ Ti/Ag PVD on contact areas ◮ Need for a masking solution

➜ jig with locating pockets.

Die Mask PVD

Before PVD After Ti/Ag PVD

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Assembly

Screen printing

◮ Ceramic laser-cut jigs for precise alignment of dies and

substrate

◮ Two sintering steps using the same temperature profile ◮ Sintering under (low) pressure (2 MPa, 240 °

C)

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Assembly

Screen printing 2- Mounting in alignment jig

◮ Ceramic laser-cut jigs for precise alignment of dies and

substrate

◮ Two sintering steps using the same temperature profile ◮ Sintering under (low) pressure (2 MPa, 240 °

C)

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Assembly

Screen printing 2- Mounting in alignment jig 3- Die-alignment jig, dies and spacer placing

◮ Ceramic laser-cut jigs for precise alignment of dies and

substrate

◮ Two sintering steps using the same temperature profile ◮ Sintering under (low) pressure (2 MPa, 240 °

C)

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Assembly

Screen printing 2- Mounting in alignment jig 3- Die-alignment jig, dies and spacer placing 4 - First sintering step

◮ Ceramic laser-cut jigs for precise alignment of dies and

substrate

◮ Two sintering steps using the same temperature profile ◮ Sintering under (low) pressure (2 MPa, 240 °

C)

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Assembly

Screen printing 2- Mounting in alignment jig 3- Die-alignment jig, dies and spacer placing 4 - First sintering step 5 - Removal of die- alignment jig

◮ Ceramic laser-cut jigs for precise alignment of dies and

substrate

◮ Two sintering steps using the same temperature profile ◮ Sintering under (low) pressure (2 MPa, 240 °

C)

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Assembly

Screen printing 2- Mounting in alignment jig 3- Die-alignment jig, dies and spacer placing 4 - First sintering step 5 - Removal of die- alignment jig 6 - Screen printing on "drain" substrate

◮ Ceramic laser-cut jigs for precise alignment of dies and

substrate

◮ Two sintering steps using the same temperature profile ◮ Sintering under (low) pressure (2 MPa, 240 °

C)

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Assembly

Screen printing 2- Mounting in alignment jig 3- Die-alignment jig, dies and spacer placing 4 - First sintering step 5 - Removal of die- alignment jig 6 - Screen printing on "drain" substrate 7 - Mounting in alignment jig

◮ Ceramic laser-cut jigs for precise alignment of dies and

substrate

◮ Two sintering steps using the same temperature profile ◮ Sintering under (low) pressure (2 MPa, 240 °

C)

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Assembly

Screen printing 2- Mounting in alignment jig 3- Die-alignment jig, dies and spacer placing 4 - First sintering step 5 - Removal of die- alignment jig 6 - Screen printing on "drain" substrate 7 - Mounting in alignment jig 8 - Second sintering step

◮ Ceramic laser-cut jigs for precise alignment of dies and

substrate

◮ Two sintering steps using the same temperature profile ◮ Sintering under (low) pressure (2 MPa, 240 °

C)

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Assembly

Screen printing 2- Mounting in alignment jig 3- Die-alignment jig, dies and spacer placing 4 - First sintering step 5 - Removal of die- alignment jig 6 - Screen printing on "drain" substrate 7 - Mounting in alignment jig 8 - Second sintering step Result

◮ Ceramic laser-cut jigs for precise alignment of dies and

substrate

◮ Two sintering steps using the same temperature profile ◮ Sintering under (low) pressure (2 MPa, 240 °

C)

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Sintering process

assembly without drying

◮ 30 min Drying step at 85 °

C, 30 min sintering at 240 ° C.

◮ 5 minutes pre-drying before assembly, to increase paste viscosity

◮ use of a glass die to observe paste spreading 19 / 25

Sintering process

assembly without drying 5 min pre-drying

◮ 30 min Drying step at 85 °

C, 30 min sintering at 240 ° C.

◮ 5 minutes pre-drying before assembly, to increase paste viscosity

◮ use of a glass die to observe paste spreading 19 / 25

Prototype

Size: 25×25 mm2

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Prototype – 2

◮ Good form factor achieved using the two-step copper

etching process

◮ Satisfying alignment ◮ Poor quality of Al-Cu attach

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Switching waveforms

0.9 1.0 1.1 1.2 time [µs] 50 50 100 150 200 Vout [V] 49.9 50.0 50.1 50.2 time [µs]

200°C

◮ Tests performed on the smallest dies (2.4×2.4 mm2, RDSon = 500 mΩ) ◮ 300 Ω Resistive load, 0.5 A current (no cooling system used) ◮ oscillations dues to external layout (and capacitances of the JFETs)

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Outline Introduction Integration of gate driver circuit Double-side Cooling Conclusion

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Conclusion

◮ Silver sintering useful for a lot more than just die attach

◮ attach of auxiliary devices (gate driver. . . ) ◮ dual-side bonding

◮ Short-term, high temperature operation demonstrated ◮ Long-term operation to be assessed:

◮ risks of silver migration? ◮ thermo-mechanical strength? ◮ what is the most suitable metal finish? 24 / 25

Conclusion

◮ Silver sintering useful for a lot more than just die attach

◮ attach of auxiliary devices (gate driver. . . ) ◮ dual-side bonding

◮ Short-term, high temperature operation demonstrated ◮ Long-term operation to be assessed:

◮ risks of silver migration? ◮ thermo-mechanical strength? ◮ what is the most suitable metal finish? 24 / 25

Conclusion

◮ Silver sintering useful for a lot more than just die attach

◮ attach of auxiliary devices (gate driver. . . ) ◮ dual-side bonding

◮ Short-term, high temperature operation demonstrated ◮ Long-term operation to be assessed:

◮ risks of silver migration? ◮ thermo-mechanical strength? ◮ what is the most suitable metal finish? 24 / 25

Thank you for your attention,

This work was funded by Euripides-Catrenes under the grant name “THOR”.

cyril.buttay@insa-lyon.fr

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