Packaging with double-side cooling capability for SiC devices, based - - PowerPoint PPT Presentation

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Packaging with double-side cooling capability for SiC devices, based - - PowerPoint PPT Presentation

Packaging with double-side cooling capability for SiC devices, based on silver sintering IECON 2018 Cyril B UTTAY 1 , Raphal R IVA 1 , Bruno A LLARD 1 ,Marie-Laure L OCATELLI 2 , Vincent B LEY 2 1 Laboratoire Ampre, Lyon, France 2 Laboratoire


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Packaging with double-side cooling capability for SiC devices, based on silver sintering

IECON 2018 Cyril BUTTAY1, Raphaël RIVA1, Bruno ALLARD1,Marie-Laure LOCATELLI2, Vincent BLEY2

1 Laboratoire Ampère, Lyon, France 2 Laboratoire LAPLACE, Toulouse, France

21/10/18

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SLIDE 2

Outline Introduction Manufacturing of the 3-D structure Results Conclusion

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SLIDE 3

Outline Introduction Manufacturing of the 3-D structure Results Conclusion

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SLIDE 4

Double Side Cooling

◮ SiC JFETs (or MOSFETs) sensitive to thermal run-away ➜ Need for efficient cooling, despite high temperature capability ◮ Standard packaging offers cooling through one side of the die only ◮ “Sandwich” package performs thermal management on both sides ◮ Requires special features for topside contact

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SLIDE 5

Double Side Cooling

◮ SiC JFETs (or MOSFETs) sensitive to thermal run-away ➜ Need for efficient cooling, despite high temperature capability ◮ Standard packaging offers cooling through one side of the die only ◮ “Sandwich” package performs thermal management on both sides ◮ Requires special features for topside contact

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SLIDE 6

Double Side Cooling

◮ SiC JFETs (or MOSFETs) sensitive to thermal run-away ➜ Need for efficient cooling, despite high temperature capability ◮ Standard packaging offers cooling through one side of the die only ◮ “Sandwich” package performs thermal management on both sides ◮ Requires special features for topside contact

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SLIDE 7

Outline Introduction Manufacturing of the 3-D structure Results Conclusion

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SLIDE 8

The proposed 3-D Structure

Vbus OUT GND JH JL

0,3 mm 0,15 mm 0,3 mm 0,15 mm

JL JH

◮ Two ceramic substrates, in “sandwich” configuration ◮ Two SiC JFET dies (SiCED) ◮ Assembled using silver sintering ◮ 25.4 mm×25.4 mm (1 in×1 in)

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SLIDE 9

Ceramic Substrates

Scale drawing for 2.4×2.4 mm2 die

SiC JFET Alumina

0.2 mm

0,3 mm

0.16 mm

0,15 mm

Copper

0.15 mm

Gate Source Source Drain

0.3 mm

◮ Etching accuracy exceeds standard design rules ◮ Double-step copper etching for die contact ➜ Custom etching technique

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SLIDE 10

Preparation of the Substrates

plain DBC board

◮ Final patterns within 50 µm of desired size ◮ Two designs, for 2.4 mm and 4 mm dies ◮ Die top metallized (PVD) with Ti/Ag ◮ Total copper thickness 300 µm, ≈ 150 µm per step

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SLIDE 11

Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating

◮ Final patterns within 50 µm of desired size ◮ Two designs, for 2.4 mm and 4 mm dies ◮ Die top metallized (PVD) with Ti/Ag ◮ Total copper thickness 300 µm, ≈ 150 µm per step

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SLIDE 12

Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development

◮ Final patterns within 50 µm of desired size ◮ Two designs, for 2.4 mm and 4 mm dies ◮ Die top metallized (PVD) with Ti/Ag ◮ Total copper thickness 300 µm, ≈ 150 µm per step

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SLIDE 13

Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching

◮ Final patterns within 50 µm of desired size ◮ Two designs, for 2.4 mm and 4 mm dies ◮ Die top metallized (PVD) with Ti/Ag ◮ Total copper thickness 300 µm, ≈ 150 µm per step

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SLIDE 14

Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching

◮ Final patterns within 50 µm of desired size ◮ Two designs, for 2.4 mm and 4 mm dies ◮ Die top metallized (PVD) with Ti/Ag ◮ Total copper thickness 300 µm, ≈ 150 µm per step

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SLIDE 15

Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching 3a - resin coating

◮ Final patterns within 50 µm of desired size ◮ Two designs, for 2.4 mm and 4 mm dies ◮ Die top metallized (PVD) with Ti/Ag ◮ Total copper thickness 300 µm, ≈ 150 µm per step

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SLIDE 16

Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching 3a - resin coating 3b - Exposure and Developpment

◮ Final patterns within 50 µm of desired size ◮ Two designs, for 2.4 mm and 4 mm dies ◮ Die top metallized (PVD) with Ti/Ag ◮ Total copper thickness 300 µm, ≈ 150 µm per step

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SLIDE 17

Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching 3a - resin coating 3b - Exposure and Developpment 4a - Photosentive film laminating

◮ Final patterns within 50 µm of desired size ◮ Two designs, for 2.4 mm and 4 mm dies ◮ Die top metallized (PVD) with Ti/Ag ◮ Total copper thickness 300 µm, ≈ 150 µm per step

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SLIDE 18

Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching 3a - resin coating 3b - Exposure and Developpment 4a - Photosentive film laminating 4b - Exposure and Development

◮ Final patterns within 50 µm of desired size ◮ Two designs, for 2.4 mm and 4 mm dies ◮ Die top metallized (PVD) with Ti/Ag ◮ Total copper thickness 300 µm, ≈ 150 µm per step

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SLIDE 19

Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching 3a - resin coating 3b - Exposure and Developpment 4a - Photosentive film laminating 4b - Exposure and Development 5 - Etching

◮ Final patterns within 50 µm of desired size ◮ Two designs, for 2.4 mm and 4 mm dies ◮ Die top metallized (PVD) with Ti/Ag ◮ Total copper thickness 300 µm, ≈ 150 µm per step

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SLIDE 20

Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching 3a - resin coating 3b - Exposure and Developpment 4a - Photosentive film laminating 4b - Exposure and Development 5 - Etching 6 - Singulating

◮ Final patterns within 50 µm of desired size ◮ Two designs, for 2.4 mm and 4 mm dies ◮ Die top metallized (PVD) with Ti/Ag ◮ Total copper thickness 300 µm, ≈ 150 µm per step

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SLIDE 21

Preparation of the Substrates

◮ Final patterns within 50 µm of desired size ◮ Two designs, for 2.4 mm and 4 mm dies ◮ Die top metallized (PVD) with Ti/Ag ◮ Total copper thickness 300 µm, ≈ 150 µm per step

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SLIDE 22

Bonding Material: Silver Sintering

Göbl, C. et al “Low temperature sinter technology Die attachment for automotive power electronic applications” proc of APE, 2006

Silver Paste ◮ Based on micro-scale silver particles (Heraeus LTS-117O2P2) ◮ Low temperature (240 ° C) sintering ◮ Low pressure (2 MPa) process No liquid phase involved: ◮ No movement of the die ◮ No bridging across terminals ◮ No height compensation thanks to wetting

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SLIDE 23

Assembly

Screen printing

◮ Ceramic jigs for alignment of dies and substrate ◮ Pre-drying of paste to prevent smearing ◮ Two sintering steps using the same temperature profile

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SLIDE 24

Assembly

Screen printing 2- Mounting in alignment jig

◮ Ceramic jigs for alignment of dies and substrate ◮ Pre-drying of paste to prevent smearing ◮ Two sintering steps using the same temperature profile

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SLIDE 25

Assembly

Screen printing 2- Mounting in alignment jig 3- Die-alignment jig, dies and spacer placing

◮ Ceramic jigs for alignment of dies and substrate ◮ Pre-drying of paste to prevent smearing ◮ Two sintering steps using the same temperature profile

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SLIDE 26

Assembly

Screen printing 2- Mounting in alignment jig 3- Die-alignment jig, dies and spacer placing 4 - First sintering step

◮ Ceramic jigs for alignment of dies and substrate ◮ Pre-drying of paste to prevent smearing ◮ Two sintering steps using the same temperature profile

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SLIDE 27

Assembly

Screen printing 2- Mounting in alignment jig 3- Die-alignment jig, dies and spacer placing 4 - First sintering step 5 - Removal of die- alignment jig

◮ Ceramic jigs for alignment of dies and substrate ◮ Pre-drying of paste to prevent smearing ◮ Two sintering steps using the same temperature profile

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SLIDE 28

Assembly

Screen printing 2- Mounting in alignment jig 3- Die-alignment jig, dies and spacer placing 4 - First sintering step 5 - Removal of die- alignment jig 6 - Screen printing on "drain" substrate

◮ Ceramic jigs for alignment of dies and substrate ◮ Pre-drying of paste to prevent smearing ◮ Two sintering steps using the same temperature profile

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SLIDE 29

Assembly

Screen printing 2- Mounting in alignment jig 3- Die-alignment jig, dies and spacer placing 4 - First sintering step 5 - Removal of die- alignment jig 6 - Screen printing on "drain" substrate 7 - Mounting in alignment jig

◮ Ceramic jigs for alignment of dies and substrate ◮ Pre-drying of paste to prevent smearing ◮ Two sintering steps using the same temperature profile

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SLIDE 30

Assembly

Screen printing 2- Mounting in alignment jig 3- Die-alignment jig, dies and spacer placing 4 - First sintering step 5 - Removal of die- alignment jig 6 - Screen printing on "drain" substrate 7 - Mounting in alignment jig 8 - Second sintering step

◮ Ceramic jigs for alignment of dies and substrate ◮ Pre-drying of paste to prevent smearing ◮ Two sintering steps using the same temperature profile

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SLIDE 31

Assembly

Screen printing 2- Mounting in alignment jig 3- Die-alignment jig, dies and spacer placing 4 - First sintering step 5 - Removal of die- alignment jig 6 - Screen printing on "drain" substrate 7 - Mounting in alignment jig 8 - Second sintering step Result

◮ Ceramic jigs for alignment of dies and substrate ◮ Pre-drying of paste to prevent smearing ◮ Two sintering steps using the same temperature profile

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SLIDE 32

Outline Introduction Manufacturing of the 3-D structure Results Conclusion

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SLIDE 33

Cross-section

◮ Very good form factor, especially around gate contact ◮ Uniform silver layers ◮ Encapsulation with parylene HT (not shown here)

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SLIDE 34

Electrical Test

0.0 0.1 0.2 0.3 0.4 Drain-Source Voltage [V] 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Drain current [A]

  • 5.0 V
  • 10.0 V
  • 15.0 V
  • 20.0 V
  • 25.0 V
  • 30.0 V

Measurement: Tektronix 371A curve tracer, room temperature

200 400 600 800 1000 Drain-Source Voltage [V] 50 100 150 200 250 300 Leakage current [nA] encapsulation breakdown VGS=-32.9 V

Keithley 2410 source & measure unit, room temperature

◮ Contact on Gate, Source and Drain of all JFETs ◮ No short-circuit between contacts

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SLIDE 35

Outline Introduction Manufacturing of the 3-D structure Results Conclusion

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SLIDE 36

Conclusion

◮ 3D structure using only high-temperature-rated materials

◮ Should be able to operate continuously at 300 ° C

◮ Silver sintering is suited to rigid sandwich structures. ◮ Proposed etching technique offers satisfying resolution ◮ Package for demonstration of technology, no cooling attempted yet

◮ Current structure fragile, new modules should integrate mechanical reliefs (solid encapsulant, direct substrate-substrate bonding. . . )

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SLIDE 37

Conclusion

◮ 3D structure using only high-temperature-rated materials

◮ Should be able to operate continuously at 300 ° C

◮ Silver sintering is suited to rigid sandwich structures. ◮ Proposed etching technique offers satisfying resolution ◮ Package for demonstration of technology, no cooling attempted yet

◮ Current structure fragile, new modules should integrate mechanical reliefs (solid encapsulant, direct substrate-substrate bonding. . . )

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SLIDE 38

Conclusion

◮ 3D structure using only high-temperature-rated materials

◮ Should be able to operate continuously at 300 ° C

◮ Silver sintering is suited to rigid sandwich structures. ◮ Proposed etching technique offers satisfying resolution ◮ Package for demonstration of technology, no cooling attempted yet

◮ Current structure fragile, new modules should integrate mechanical reliefs (solid encapsulant, direct substrate-substrate bonding. . . )

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SLIDE 39

Conclusion

◮ 3D structure using only high-temperature-rated materials

◮ Should be able to operate continuously at 300 ° C

◮ Silver sintering is suited to rigid sandwich structures. ◮ Proposed etching technique offers satisfying resolution ◮ Package for demonstration of technology, no cooling attempted yet

◮ Current structure fragile, new modules should integrate mechanical reliefs (solid encapsulant, direct substrate-substrate bonding. . . )

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SLIDE 40

Thank you for your attention.

This work was supported through the grants EPAHT (French National Fundation for Aeronautic and Space Research - FNRAE) and THOR (EURIPIDES-CATRENE).

cyril.buttay@insa-lyon.fr

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