Sequential circuits If the same input may produce different output - - PowerPoint PPT Presentation

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Sequential circuits If the same input may produce different output - - PowerPoint PPT Presentation

Apr 06, 2023 262 likes •768 views

Sequential circuits If the same input may produce different output signal, we have a sequential logic circuit. It must then have an internal memory that allows the Same input can produce different output output to be affected by both the

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SLIDE 1

Sequential circuits

William Sandqvist william@kth.se

If the same input may produce different output signal, we have a sequential logic circuit. It must then have an internal memory that allows the

  • utput to be affected by both

the current and previous inputs!

Logic circuit

Same input can produce different output

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SLIDE 2

Moore-machine

William Sandqvist william@kth.se NEXT STATE DECODER STATE REGISTER OUTPUT DECODER

State

Clk

Input- signals Output- signals

For Moore machine the outputs depends on the inputs and the internal state. The internal memory is the state register consisting of D flip-flops.

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SLIDE 3

William Sandqvist william@kth.se

State register D-flip-flops

State register D flip-flops slows down the race between signals until the value is stable. (Compare with the tollbooth).

NEXT STATE DECODER

STATE REGISTER OUTPUT DECODER Output- signals Input- signals

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SLIDE 4

William Sandqvist william@kth.se

State register D-flip-flops

NEXT STATE DECODER

STATE REGISTER OUTPUT DECODER Output- signals Input- signals

? ? State register D flip-flops slows down the race between signals until the value is stable. (Compare with the tollbooth).

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SLIDE 5

William Sandqvist william@kth.se

NEXT STATE DECODER

STATE REGISTER OUTPUT DECODER Output- signals Input- signals

? ?

State register D-flip-flops

! ! State register D flip-flops slows down the race between signals until the value is stable. (Compare with the tollbooth).

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SLIDE 6

Quickie Question … flip-flop

Which of the following timing diagram is valid for a edge-triggered D flip-flop?

Alt: A Alt: B Alt: C

D Q Clock In1 In2 Out In1 In2 Out In1 In2 Out In1 In2 Out

William Sandqvist william@kth.se

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SLIDE 7

Quickie Question … flip-flop

Alt: B Alt: C

D Q Clock In1 In2 Out In1 In2 Out In1 In2 Out In1 In2 Out

William Sandqvist william@kth.se

Alt: A

D is copied to output at the edge, when Clock goes from 0 to 1

Which of the following timing diagram is valid for a edge-triggered D flip-flop?

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SLIDE 8

Quickie Question … Latch

Which of the following timing diagram is valid for a D Latch?

William Sandqvist william@kth.se

Alt: A Alt: B Alt: C

D Q Enable In1 In2 Out In1 In2 Out In1 In2 Out In1 In2 Out

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SLIDE 9

William Sandqvist william@kth.se

Alt: A Alt: B Alt: C

D Q Enable In1 In2 Out In1 In2 Out In1 In2 Out In1 In2 Out

D is connected to output when Enable is 1, and is locked when Enable is 0

Quickie Question … Latch

Which of the following timing diagram is valid for a D Latch?

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SLIDE 10

Design: ”two consecutive”

William Sandqvist william@kth.se

Sequence Detector. If w has been 1 in two (or more) consecutive clock then z = 1. w w z C Clk Specification Sequence circuit has an input w and an output z If input w has been 1 in during the current and previous clock cycle then z will be set to 1 Use a Moore machine with D-flip-flops to realizing the design.

(Reset)

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SLIDE 11

Statediagram ”two consecutive”

William Sandqvist william@kth.se

C z 1 =

⁄

Reset B z 0 =

⁄

A z 0 =

⁄

w = w 1 = w 1 = w = w = w 1 =

State State transition State name Output value A zero B single one C two or moore consecutive

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SLIDE 12

State table

William Sandqvist william@kth.se

Present Next state Output state

w = 0 w = 1 z

A A B B A C C A C 1

Three states – two flip-flops needed to hold state numbers!

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SLIDE 13

”two consecutive” as Moore- machine

William Sandqvist william@kth.se

Combinational circuit Combinational circuit Clock y

2

z w y

1

Y

1

Y

2

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SLIDE 14

Designdecissions

William Sandqvist william@kth.se

  • The designer must decide which flip-flops?

to be used D-, T-, or JK-flip-flop

  • The designer must choose the code for each

state

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SLIDE 15

Designbeslut

William Sandqvist william@kth.se

This time:

  • D-flip-flop
  • State code A = 00, B = 01, C = 10
  • The code word 11 should not occur.

We choose don’t care.

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SLIDE 16

Coded state table

William Sandqvist william@kth.se

Present Next state state w = 0 w = 1 Output z A 00 00 01 B 01 00 10 C 10 00 10 1 11 dd dd d

1 2Y

Y

1 2y

y

1 2Y

Y

2 1 2 1 2 1

( ) ( ) Y Y f y y w z f y y = =

A = 00 B = 01 C = 10

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SLIDE 17

Next state decoder

William Sandqvist william@kth.se

) ( ) ( ) ( ) (

1 2 1 2 1 1 2 2 1 2 1 2

y y f z w y y f Y w y y f Y w y y f Y Y = = = =

The Next state decoder consists of two logic networks available as input network to the two flip-flops. In order to minimize logic networks, we enter the truth tables in the form of Karnaugh maps.

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SLIDE 18

From coded statetable to Karnaughmap

William Sandqvist william@kth.se

w 00 01 11 10 1 1 y 2 y 1 d d

Y

1 = wy 1y 2

1

Y

w 00 01 11 10 1 d 1 d y 2 y 1 1

2

Y

) (

2 1 2 1 2

y y w wy wy Y + = = + =

) ( ) ( ) (

1 2 1 1 2 2 1 2 1 2

w y y f Y w y y f Y w y y f Y Y = = =

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SLIDE 19

Output decoder

William Sandqvist william@kth.se

1 1 d y 1 1 y 2

z = y2

) (

1 2y

y f z =

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SLIDE 20

Implementation

William Sandqvist william@kth.se

z = y2 Y

1 = wy 1y 2

) (

2 1 2 1 2

y y w wy wy Y + = = + =

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SLIDE 21

Timing diagram ”two consecutive”

William Sandqvist william@kth.se

t t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

1 1 1 1 Clock w y

1

y

2

1 z

State transitions

  • ccurs only on

the positive clock edge!

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SLIDE 22

In other terms

William Sandqvist william@kth.se

) ( ) ( ) (

1 2 1 1 2 2 1 2 1 2

w y y f y w y y f y w y y f y y = = =

+ + + +

Exercises and Hemert-book:

+

y y

Present state Next state

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SLIDE 23

With another lineup

William Sandqvist william@kth.se

) ( ) ( ) (

1 2 1 1 2 2 1 2 1 2

w y y f y w y y f y w y y f y y = = =

+ + + +

You could directly write down the codet state table as a ”Karnaugh map”. In exercises we use this method

A B C

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SLIDE 24

William Sandqvist william@kth.se

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SLIDE 25

Mealy-machine

William Sandqvist william@kth.se NEXT STATE DECODER STATE REGISTER OUTPUT DECODER State

Clk

Input- signals Output- signals

In a Mealy Machine output signals depends on both the current state and the inputs.

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SLIDE 26

State diagram Mealy

William Sandqvist william@kth.se

A w 0 = z 0 =

⁄

w 1 = z 1 =

⁄

B w 0 = z 0 =

⁄

Reset w 1 = z 0 =

⁄

Value of output signal State name Value of input signal

”Two consecutive”

  • The state diagram for the Mealy-machine only

needs two states

  • Output signal depends booth on states and input.
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SLIDE 27

State table

William Sandqvist william@kth.se

Present Next state Output z state w = 0 w = 1 w = 0 w = 1 A A B B A B 1

A w 0 = z 0 =

⁄

w 1 = z 1 =

⁄

B w 0 = z 0 =

⁄

Reset w 1 = z 0 =

⁄

Two states – only one flip-flop is needed!

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SLIDE 28

Coded state table

William Sandqvist william@kth.se

Present Next state Output state w = 0 w = 1 w = 0 w = 1 y Y Y z z A 1 B 1 1 1

) ( ) ( w y f z w y f Y = = yw z w Y = =

Directly from the table: A = 0 B = 1

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SLIDE 29

Implementation

William Sandqvist william@kth.se Clock Resetn D Q Q w z y

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SLIDE 30

Timing diagram

William Sandqvist william@kth.se t t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

1 1 1 1 Clock y w z

  • The output may change during the clock period, since it

is a function of the input signal

  • Compared to Moore machine the Mealy machine is

moore 'responsive' (bit sequence is detected in t4 compared to t5 for the Moore-machine)

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SLIDE 31

Mealy with output register

William Sandqvist william@kth.se

Clock Resetn D Q Q w z y D Q Q Z

  • The disadvantage of the Mealy machine is that the
  • utput can be changed during the entire clock period
  • You can add a register (flip-flop) at the end so to

synchronize the output with the clock edge

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SLIDE 32

Timing diagram with output register

William Sandqvist william@kth.se

t t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

1 1 1 1 Clock y w z 1 Z

With an output register there are no longer any differences between the timing diagrams!

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SLIDE 33

Moore vs Mealy

William Sandqvist william@kth.se

  • Moore-machine output values ​depend only
  • n the current state
  • Mealy-machine output values ​depend on the

current state and the values ​of the input signals

  • Mealy-machine often uses fewer states
  • Mealy-machine output signals are not inte

synchronized with the clock, why you often has to add an output register

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SLIDE 34

William Sandqvist william@kth.se

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SLIDE 35

Selection of state encoding

William Sandqvist william@kth.se

Selection of state encoding can play a major role in implementation as it affects the logic for

  • Next-state-decoder
  • Output decoder
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SLIDE 36

”two consecutive” state diagram

William Sandqvist william@kth.se

C z 1 =

⁄

Reset B z 0 =

⁄

A z 0 =

⁄

w = w 1 = w 1 = w = w = w 1 =

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SLIDE 37

State code = Binary

William Sandqvist william@kth.se

Present Next state state w = 0 w = 1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z A 00 00 01 B 01 00 10 C 10 00 10 1 11 dd dd d A = 00 B = 01 C = 10 11

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SLIDE 38

Realization (Binary code)

William Sandqvist william@kth.se

2 D-flip-flops 2 AND-gates 1 OR-gate

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SLIDE 39

State code = Gray code

William Sandqvist william@kth.se

Present Next state state w = 0 w = 1 Output y

2

y

1

Y

2

Y

1

Y

2

Y

1

z A 00 00 01 B 01 00 11 C 11 00 11 1 10 dd dd d

  • In the Gray-code only one bit at a time is changed, eg. 00,

01, 11, 10

  • Gray-code is good for counters

A = 00 B = 01 C = 11 10

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SLIDE 40

Realization (Gray code)

William Sandqvist william@kth.se

D Q Q D Q Q Y

2

Y

1

w Clock z y

1

y

2

Resetn

2 D-flip-flops 1 AND-gate As the Gray code did well in this case this sequential circuit has

  • bviously has

“counting properties”

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SLIDE 41

One-Hot-encoding

William Sandqvist william@kth.se

  • One-hot-encoding uses one flop-flop

per state

  • For each state one bit is ‘hot’ (1), all
  • ther bits are 0,
  • eg. 0001, 0010, 0100, 1000
  • One-hot encoding minimizes the

combinatorial logic, but increases the number of flip-flops!

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SLIDE 42

What code should be chosen?

William Sandqvist william@kth.se

  • There is not a code that is the best in every

situation, it all depends on the state diagram

  • You can also have your 'own codes' that fits

into the design, eg. 00, 11, 10, 01

slide-43
SLIDE 43

William Sandqvist william@kth.se

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SLIDE 44

William Sandqvist william@kth.se

  • Example. - wait - cw - wait - ccw -

q1 q2

1 3 1 1 2 1 1

1 2 1 2 1 2 1 2

q q Z q q Z q q Z q q Z

wait cw wait ccw With this state encoding (Graycode) we need no output decoder!

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SLIDE 45

William Sandqvist william@kth.se

  • Example. - wait - cw - wait - ccw -

Can you can set up the encoded state table and Karnaugh maps by your self … ? q1 q2

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SLIDE 46

William Sandqvist william@kth.se

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SLIDE 47

William Sandqvist william@kth.se

  • Example. - wait - cw - wait - ccw -

q1 q2

2 1 1 2 1 2

q i q i q q i q i q + = + =

+ +

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SLIDE 48

William Sandqvist william@kth.se

  • wait - cw - wait - ccw -

2 1 1 2 1 2

q i q i q q i q i q + = + =

+ +

With NAND-gates

slide-49
SLIDE 49

William Sandqvist william@kth.se