SEQ part 3 Samira Khan The slides are prepared by Charles Reiss 1

Review each instruction takes one cycle send new values to state components 2 read values from previous cycle control what is sent with MUXes

simple ISA 4: mov-to-register irmovq $constant, %rYY rrmovq %rXX, %rYY mrmovq 10(%rXX), %rYY 3

mov-to-register CPU irmovq V, rB immediate + (ALU) +2 +10 rrmovq rA, rB 2 0 rA rB 3 convert 0 F rB mrmovq D(rB), rA 5 0 rA rB V D opcode MUX PC dstE Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] next R[dstE] split dstM next R[dstM] Data Mem. ZF/SF Data in Addr in Data out 4

simple ISA 4B: mov irmovq $constant, %rYY rrmovq %rXX, %rYY mrmovq 10(%rXX), %rYY rmmovq %rXX, 10(%rYY) 5

mov CPU 0 rA rB from convert opcode rrmovq rA, rB 2 0 rA rB irmovq V, rB 3 0 F rB mrmovq D(rB), rA 5 rmmovq rA, D(rB) 0xF 4 0 rA rB V D D valP valC valB valA valE valM write enable +10 PC Data Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM] Mem. +2 ZF/SF Data in Addr in Data out split MUX convert opcode immediate immediate + 6

mov CPU 0xF opcode immediate immediate + (ALU) +2 +10 write enable MUX from convert opcode fetch decode execute memory writeback PC update convert split PC dstE Instr. Mem. register fjle srcA srcB R[srcA] R[srcB] next R[dstE] Data out dstM next R[dstM] Data Mem. ZF/SF Data in Addr in 7

Stages conceptual division of instruction: fetch — read instruction memory, split instruction, compute length decode — read register fjle execute — arithmetic (including of addresses) memory — read or write data memory write back — write to register fjle PC update — compute next value of PC 8

stages and time 1; then 2, 3, and 4 at almost the same time something else f. 1; then 2; then 3 and 4 at almost the same time e. 1; then 3; then 2; then 4 d. 1; then 2; then 3; then 4 c. b. fetch / decode / execute / memory / write back / PC update 1; then 2, 3, and 4 in any order a. Hint: recall how registers, register fjles, memory works 4. PC changes 3. %rsp changes 2. memory changes 1. instruction read Order when these events happen pushq %rax instruction: 9

stages example: nop write back input wire to PC register name of a wire from instruction memory part of output wires stage PC update memory decode fetch nop 10 icode : ifun ← M 1 [ PC ] valP ← PC + 1 ← means putting a value on a wire ← means putting value on PC ← valP

stages example: nop/jmp stage valP valC MUX PC PC update write back memory decode fetch jmp dest nop 11 icode : ifun ← M 1 [ PC ] icode : ifun ← M 1 [ PC ] valP ← PC + 1 valC ← M 8 [ PC + 1] PC ← valP PC ← valC

stages example: rmmovq/mrmovq assignment means: write back PC update assignment means: setting register number input to register fjle and naming output wires of register fjle but would be harmless setting address wires to valE and memory setting value input wires to valA and setting memory write enable to 1 assignment means: naming the output of the data memory assignment means: setting register fjle input wires to valM setting register fjle write register number stage 12 rmmovq rA, D(rB) execute mrmovq D(rB), rA fetch decode icode : ifun ← M 1 [ PC ] icode : ifun ← M 1 [ PC ] rA : rB ← M 1 [ PC + 1] rA : rB ← M 1 [ PC + 1] valP ← PC + 10 valP ← PC + 10 valC ← M 8 [ PC + 2] valC ← M 8 [ PC + 2] valA ← R [ rA ] valB ← R [ rB ] valB ← R [ rB ] setting address wires to valE and reading R [ rA ] not needed valE ← valB + valC valE ← valB + valC M 8 [ valE ] ← valA valM ← M 8 [ valE ] R [ rA ] ← valM PC ← valP PC ← valP

SEQ part 3 Samira Khan The slides are prepared by Charles Reiss 1 - PowerPoint PPT Presentation

SEQ part 3 Samira Khan The slides are prepared by Charles Reiss 1 Review each instruction takes one cycle send new values to state components 2 read values from previous cycle control what is sent with MUXes simple ISA 4: mov-to-register

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