SEQ part 3 / HCLRS one cycle per instruction in this design valP - PowerPoint PPT Presentation

SEQ part 3 / HCLRS one cycle per instruction in this design valP — PC + (instr length) compute next instruction address: valC — call target or mov displacement rA, rB — register numbers icode:ifun — opcode split into seperate wires: read instruction memory at PC SEQ: instruction fetch 2 change) rising edge of clock triggers state change (register/memory values calculations between rising edges of clock actual timing — clock signal 1 consider what every instruction does for a particular stage for now: ease processor design conceptual stages single cycle processor design strategy last time 1 21 September 2017: correct a couple instances of ‘HCL2D’ to ‘HCLRS’ 21 September 2017: slide 26: need MUX for 0 ALU input 21 September 2017: slide 23: add input to pre R[dstE] mux for irmovq not PC 21 September 2017: data memory value MUX input for call is PC + 10, Changes made in this version not seen in fjrst lecture: Changelog 3

instruction fetch Instr. valP exercise: which of these instructions can this not work for? nop , addq , mrmovq , popq , call , 6 instruction decode (1) PC Mem. length register fjle srcA srcB R[srcA] R[srcB] dstE + instr. dstM 0 rB ALU aluA aluB valE 8 add/sub PC + 10 xor/and (function of instr.) write? function of opcode next R[dstE] next R[dstM] %rsp of opcode add/sub xor/and (function of instr.) write? function PC + 10 8 instr. length + valP exercise: which of these instructions can this not work for? nop , addq , mrmovq , popq , call , 0 valE Data valC Mem. ZF/SF Stat Data in Addr in Data out 0xF aluB 0xF %rsp %rsp rA rB ALU aluA rA %rsp PC ALU 0xF 0xF %rsp %rsp rA rB aluA Data out aluB valE 8 0 add/sub xor/and valC Addr in of instr.) R[srcB] Instr. Mem. register fjle srcA srcB R[srcA] dstE Data in next R[dstE] dstM next R[dstM] Data Mem. ZF/SF Stat (function write? 0xF Mem. R[srcB] dstE next R[dstE] dstM next R[dstM] Data ZF/SF srcB Stat Data in Addr in Data out valC 0xF R[srcA] srcA function 4 of opcode PC + 10 instr. length + valP SEQ: instruction “decode” register fjle read registers valA, valB — register values 5 instruction decode (1) PC Instr. Mem. 6

SEQ: srcA, srcB rB srcB srcA instruction SEQ: possible registers to read 8 icode logic function F (none) %rsp srcB none MUX %rsp rA pushq , popq %rsp none? call , ret rB rA rmmovq , OP q halt , nop , j CC , irmovq none none pushq , popq icode logic function F (none) %rsp rB srcB MUX %rsp rA %rsp cmovCC , rrmovq none? call , ret rB rA rmmovq , OP q rB none mrmovq none rA rB mrmovq always read rA, rB? srcB rmmovq , OP q rB none mrmovq none rA cmovCC , rrmovq none none halt , nop , j CC , irmovq srcA rB instruction SEQ: possible registers to read 7 MUX controlled by icode extra signals: srcA, srcB — computed input register ret call pop push rA Problems: rA call , ret none icode rA cmovCC , rrmovq none none halt , nop , j CC , irmovq srcB srcA instruction SEQ: possible registers to read 8 logic function none? F (none) %rsp rB srcB MUX %rsp rA pushq , popq %rsp 8

instruction decode (2) R[srcA] Addr in Data in Stat ZF/SF Mem. Data next R[dstM] dstM next R[dstE] dstE R[srcB] srcB valC srcA register fjle Mem. Instr. PC execute (1) 11 NOT dstE 0xF rB Data out 0xF cc (function nop , addq , mrmovq , popq , call , exercise: which of these instructions can this not work for? valP + length instr. PC + 10 of opcode function write? of instr.) xor/and 0xF add/sub 0 8 valE aluB aluA ALU rB rA %rsp %rsp (from instr) ( l ) SF PC Mem. rA %rsp %rsp 0xF 0xF valC Data out Addr in Data in Stat ZF/SF Data ALU next R[dstM] dstM next R[dstE] dstE R[srcB] R[srcA] srcB srcA register fjle Mem. Instr. rB aluA ( le ) SF | ZF + ( always ) 1 using condition codes: cmov* 10 write new condition codes Cnd — condition codes based on ifun (instruction type for jCC/cmovCC) read prior condition codes valE — ALU output perform ALU operation (add, sub, xor, and) SEQ: execute 9 valP length aluB instr. PC + 10 of opcode function write? of instr.) (function xor/and add/sub 0 8 valE 12

execute (1) R[srcB] Data out Addr in Data in Stat ZF/SF Mem. Data next R[dstM] dstM next R[dstE] dstE R[srcA] 0xF srcB srcA register fjle Mem. Instr. PC execute (2) 13 computed ALU input values ret call valC 0xF pushq write? valM — value read from memory (if any) read or write data memory SEQ: Memory 14 valP + length instr. PC + 10 of opcode function of instr.) %rsp (function xor/and add/sub 0 8 valE aluB aluA ALU rB rA %rsp popq no, constants: (rsp +/- 8) PC ZF/SF rB rA %rsp %rsp 0xF 0xF valC Data out Addr in Data in Stat Mem. aluA Data next R[dstM] dstM next R[dstE] dstE R[srcB] R[srcA] srcB srcA register fjle Mem. Instr. ALU aluB rmmovq valP mrmovq valC valB aluB MUX no, inputs from instruction: (Displacement + rB) ALU inputs always valA, valB (register values)? SEQ: ALU operations? 12 nop , addq , mrmovq , popq , call , exercise: which of these instructions can this not work for? + valE length instr. PC + 10 of opcode function write? of instr.) (function xor/and add/sub 0 8 15 extra signals: aluA, aluB

memory (1) tricky cases: call , push read/write — read enable? write enable? Addr — address mostly ALU output tricky cases: popq , ret Data — value to write mostly valB 17 16 memory (2) PC Instr. Mem. register fjle srcA srcB SEQ: control signals for memory nop , rmmovq , mrmovq , popq , call , R[srcB] of instr.) valE 8 0 add/sub xor/and (function write? exercise: which of these instructions can this not work for? function of opcode PC + 10 instr. length + valP R[srcA] dstE aluA of instr.) valE 8 0 add/sub xor/and (function write? aluA function of opcode PC + 10 instr. length + valP aluB ALU next R[dstE] Data in dstM next R[dstM] Data Mem. ZF/SF Stat Addr in rB Data out valC 0xF 0xF %rsp %rsp rA aluB ALU PC ALU 0xF 0xF %rsp %rsp rA rB aluA Data out aluB valE 8 0 add/sub xor/and (function valC Addr in write? R[srcB] Instr. Mem. register fjle srcA srcB R[srcA] dstE Data in next R[dstE] dstM next R[dstM] Data Mem. ZF/SF Stat of instr.) function rB Data in dstM next R[dstM] Data Mem. ZF/SF Stat Addr in dstE Data out valC 0xF 0xF %rsp %rsp rA next R[dstE] R[srcB] of opcode nop , rmmovq , mrmovq , popq , call , PC + 10 instr. length + valP exercise: which of these instructions can this not work for? 16 R[srcA] memory (1) PC Instr. Mem. register fjle srcA srcB 18

SEQ: write back Data out valE aluB aluA ALU rB rA %rsp %rsp 0xF 0xF valC Addr in 0 Data in Stat ZF/SF Mem. Data next R[dstM] dstM next R[dstE] dstE R[srcB] R[srcA] 8 add/sub srcA 20 %rsp F rB dstE MUX write disable — use dummy register number 0xF dstM, dstE two register numbers valM (memory output), valE (ALU output) two write inputs — two needed by popq SEQ: control signals for WB nop , pushq , mrmovq , popq , call , xor/and exercise: which of these instructions can this not work for? valP + length instr. PC + 10 of opcode function write? of instr.) (function srcB register fjle write registers dstM 0xF 0xF valC Data out Addr in Data in Stat ZF/SF Mem. Data next R[dstM] next R[dstE] %rsp dstE R[srcB] R[srcA] srcB srcA register fjle Mem. Instr. PC write back (1) 19 %rsp rA Mem. of opcode Instr. PC write back (1) 20 nop , pushq , mrmovq , popq , call , exercise: which of these instructions can this not work for? valP + length instr. PC + 10 function rB write? of instr.) (function xor/and add/sub 0 8 valE aluB aluA ALU 21

write back (2) srcB write back (3b) PC Instr. Mem. register fjle srcA R[srcA] valP R[srcB] dstE next R[dstE] dstM next R[dstM] Data 23 + ZF/SF xor/and aluA aluB valE 8 0 add/sub (function length of instr.) write? function of opcode PC + 10 instr. Mem. Stat rB length of instr.) write? function of opcode PC + 10 instr. + xor/and valP 24 SEQ: Update PC choose value for PC next cycle (input to PC register) usually valP (following instruction) exceptions: call , j CC , ret (function add/sub Data in %rsp Addr in Data out valC 0xF 0xF %rsp rA 0 rB ALU aluA aluB valE 8 ALU rA PC rB valC 0xF 0xF %rsp %rsp rA ALU Addr in aluA aluB valE 8 0 add/sub Data out Data in (function R[srcB] Instr. Mem. register fjle srcA srcB R[srcA] dstE Stat next R[dstE] dstM next R[dstM] Data Mem. ZF/SF xor/and of instr.) %rsp Stat next R[dstE] dstM next R[dstM] Data Mem. ZF/SF Data in R[srcB] Addr in Data out valC 0xF 0xF %rsp dstE R[srcA] write? valP function of opcode PC + 10 instr. length + 22 srcB write back (3a) PC Instr. Mem. register fjle srcA 25