Runtime Model Predictive Verification on Embedded Platforms 1 Pei - - PowerPoint PPT Presentation

runtime model predictive verification
SMART_READER_LITE
LIVE PREVIEW

Runtime Model Predictive Verification on Embedded Platforms 1 Pei - - PowerPoint PPT Presentation

Runtime Model Predictive Verification on Embedded Platforms 1 Pei Zhang, Jianwen Li, Joseph Zambreno, Phillip H. Jones, Kristin Yvonne Rozier Presenter: Pei Zhang Iowa State University peizhang@iastate.edu September 28, 2018 1 Work supported


slide-1
SLIDE 1

Runtime Model Predictive Verification

  • n Embedded Platforms 1

Pei Zhang, Jianwen Li, Joseph Zambreno, Phillip H. Jones, Kristin Yvonne Rozier

Presenter: Pei Zhang Iowa State University peizhang@iastate.edu

September 28, 2018

1Work supported by NASA ECF NNX16AR57G and NSF CAREER Award

CNS-1552934.

1 / 32

slide-2
SLIDE 2

Overview

1

Introduction Overview

2

Preliminary State Space Model

3

Methodology Hardware Monitor Model Predictive Runtime Verification

4

Evaluation Simulation of MPRV Disturbance Effect WCET Analysis

5

Conclusion

6

Related Work

2 / 32

slide-3
SLIDE 3

Introduction

Motivation

Light weight monitor for embedded platform; Unobstrusive to a certified safety-critical system; Providing timely information; Runtime safety monitor

3 / 32

slide-4
SLIDE 4

Introduction Overview

Overview of Design Architecture

Future Time Monitor

AP1 … APn

Supervisory Controller Sensor Controllers

Environment

On-chip

Control Feedback

Conversion Function

Figure: High level architecture of model predictive runtime verication.

4 / 32

slide-5
SLIDE 5

Introduction Overview

Overview of Design Architecture

Predictor Future Time Monitor

AP1 APn

Supervisory Controller Controller Model Model Predictor Sensor Controllers

Environment

On-chip

Control Feedback AP

1 AP m

Figure: High level architecture of model predictive runtime verication.

5 / 32

slide-6
SLIDE 6

Preliminary

Extending LTL for Safety Properties: MLTL

Mission-Time Linear Temporal Logic (MLTL) reasons about bounded timelines: finite set of atomic propositions {p q} Boolean connectives: ¬, ∧, ∨, and → temporal connectives with time bounds: Symbol Operator Timeline

[2,6]p Always[2,6]

1 2 3 4 5 6 7 8 p p p p p

[0,7]p Eventually[0,7]

1 2 3 4 5 6 7 8 p

pU[1,5]q Until[1,5]

1 2 3 4 5 6 7 8 p p q

pR[3,8]q Release[3,8]

p,q 1 2 3 4 5 6 7 8 q q q

6 / 32

slide-7
SLIDE 7

Preliminary

Model Predictive Function F ∶ Σ → Σ∗. Definition (Predictive MLTL Semantics) Let π be a finite trace over Σ∗. The predictive truth value of the MLTL formula ϕ with respect to π, denoted as [π ⊧ ϕ]p, is an element of {true,false,?} defined as follows: [π ⊧ ϕ]p = ⎧ ⎪ ⎪ ⎪ ⎪ ⎨ ⎪ ⎪ ⎪ ⎪ ⎩ true if ∀π′ ∈ Σ∗ ⋅ (π ⋅ F(π) ⋅ π′) ⊧ ϕ; false if ∀π′ ∈ Σ∗ ⋅ (π ⋅ F(π) ⋅ π′) / ⊧ ϕ; ? (skip) Otherwise.

7 / 32

slide-8
SLIDE 8

Preliminary State Space Model

State Space Model

A discrete state-space model defines what state a system will be in

  • ne-time step into the future:

xk+1 = Axk + Buk (1) yk = Cxk + Duk (2) xk represents the state of the system at time k uk represents the input acting on the system at time k yk represents outputs of the system at time k A is a matrix that defines the internal dynamics of the system B is a matrix that defines how the input acting upon the system impact its state C is a matrix that transforms states of the system into outputs (yk)

8 / 32

slide-9
SLIDE 9

Methodology Hardware Monitor

Abstract Syntax Tree (AST)

Q: How can we check MLTL satisfication in hardware? Compile the MLTL formula into assembly code: e.g. ◻[0,2](!a0) Line 0 ∶ s0 ← load (a0,time) Line 1 ∶ s1 ← ¬ s0 Line 2 ∶ s2 ← ◻[0,2] s1 Each instruction are stored in a data structure called Shared Connection Queue (SCQ).

9 / 32

slide-10
SLIDE 10

Methodology Hardware Monitor

Computation Core

Instruction Memory PC RAW Sensor Signals (binary) AP[1] AP[N]

...

ATOMICs v1 v2

...

Var Mem FSM

L

LOAD

¬

NEGATE GLOBAL/FUTURE AND/OR UNTIL CORE RAM Filters I1 I2

...

SCQ I1 I2

... 𝜐e

I1 I2

...

PTR Queue Management L

¬ □/◇ ∧/∨

U

∧/∨

□/◇

U

(a) Observer Processing Core.

Search SCQ Observer Algorithm Increase PC Find Data Fetch Instruction Empty Write Back

(b) State machine transitions. Figure: Hardware design for embedded MLTL observer processor.

10 / 32

slide-11
SLIDE 11

Methodology Model Predictive Runtime Verification

Model Predictive Runtime Verification Processing Flow

Read Sensor Runtime Verification Cache Restore

1 2 3 4 5 6

Model Prediction

Step 1 Convert sensor data into atomic propositions (APs) using predefined atomic conversion functions.

11 / 32

slide-12
SLIDE 12

Methodology Model Predictive Runtime Verification

Model Predictive Runtime Verification Processing Flow

Read Sensor Runtime Verification Cache Restore

1 2 3 4 5 6

Model Prediction

Step 2 Observer processing core conducts runtime verification over the newly received APs.

12 / 32

slide-13
SLIDE 13

Methodology Model Predictive Runtime Verification

Model Predictive Runtime Verification Processing Flow

Read Sensor Runtime Verification Cache Restore

1 2 3 4 5 6

Model Prediction

Step 3 Model Predictive Control (MPC) for a specified prediction horizon length is executed to estimate future states of the system.

13 / 32

slide-14
SLIDE 14

Methodology Model Predictive Runtime Verification

Model Predictive Runtime Verification Processing Flow

Read Sensor Runtime Verification Cache Restore

1 2 3 4 5 6

Model Prediction

Step 4 Contents of the SCQs are cached.

14 / 32

slide-15
SLIDE 15

Methodology Model Predictive Runtime Verification

Model Predictive Runtime Verification Processing Flow

Read Sensor Runtime Verification Cache Restore

1 2 3 4 5 6

Model Prediction

Step 5 Observer processing core conducts runtime verification over the generated trace of estimated future system states.

15 / 32

slide-16
SLIDE 16

Methodology Model Predictive Runtime Verification

Model Predictive Runtime Verification Processing Flow

Read Sensor Runtime Verification Cache Restore

1 2 3 4 5 6

Model Prediction

Step 6 Restore cached SCQs contents. Thereby, placing the observer processing core back into its original state.

16 / 32

slide-17
SLIDE 17

Methodology Model Predictive Runtime Verification

Model Predictive Runtime Verification Processing Flow

Read Sensor Runtime Verification Cache Restore

1 2 3 4 5 6

Model Prediction

Step 7 Return to step 1), once the next sensor sampling period starts.

17 / 32

slide-18
SLIDE 18

Evaluation Simulation of MPRV

MPRV on Moving a Point Mass

10 20 30 40 50 60

Time (s)

0.0 0.5 1.0 1.5 2.0

Position (m)

position planned trajectory

Figure: Model predictive control of the height of a point mass.

Control input force ∈ [-1N, 1N]. Cost weighting: 2 with the error in mass position and 1 with its speed. Prediction horizon: 100. Controller actuation update rate to 10 Hz. a0: absolute speed < 0.1m/s. a1: absolute value of trajectory error < 0.08m.

18 / 32

slide-19
SLIDE 19

Evaluation Simulation of MPRV

False True ([5]a1) ∧ a0 10 20 30 40 50 60

Time (sec)

No Prediction Predict 10 (1.0s) Predict 50 (5.0s)

Figure: MPRV responsiveness for different prediction horizons: No prediction, 10 steps

(1s), 50 steps (5s).

False True a1 U[5,20]a0 10 20 30 40 50 60

Time (sec)

No Prediction Predict 10 (1.0s) Predict 50 (5.0s)

19 / 32

slide-20
SLIDE 20

Evaluation Simulation of MPRV

Disturbance

10 20 30 40 50 60

Time (s)

0.0 0.5 1.0 1.5 2.0

Position (m)

position planned trajectory

Figure: Unexpected disturbance taken place during control. The disturbance is marked

in by the yellow rectangle.

an external disturbance force being applied at time 14.6s and 35.0s. a0: absolute speed < 0.5m/s. a1: absolute value of trajectory error < 0.04m.

20 / 32

slide-21
SLIDE 21

Evaluation Simulation of MPRV

Disturbance

10 20 30 40 50 60

Time (s)

0.0 0.5 1.0 1.5 2.0

Position (m)

position planned trajectory False True a1 ∧ [15]a0 10 20 30 40 50 60

Time (sec)

No Prediction Predict 50 (5.0s)

Figure: Comparasion between MPRV and normal RV with disturbance.

21 / 32

slide-22
SLIDE 22

Evaluation Simulation of MPRV

Disturbance

10 20 30 40 50 60

Time (s)

0.0 0.5 1.0 1.5 2.0

Position (m)

position planned trajectory False True a1 ∧ [15]a0 10 20 30 40 50 60

Time (sec)

No Prediction Predict 50 (5.0s)

Figure: Comparasion between MPRV and normal RV with disturbance.

22 / 32

slide-23
SLIDE 23

Evaluation Simulation of MPRV

Utilize the MPRV Predictions under Disturbance

1 Case 1: Disturbance instantly breaks MLTL rule. 2 Case 2: Disturbance does not instantly break the MLTL rule. 3 Case 3: Disturbance adverts the system from breaking the

MLTL in the future.

23 / 32

slide-24
SLIDE 24

Evaluation Simulation of MPRV

Sensor Noise and Prediction Horizon Length

0.0 0.2 0.4 0.6 Noise Standard Deviation 0% 20% 40% 60% 80% 100% Accuracy

a0 a1 a2 a4 [15]a1 ◻[15]a1 ◻[15]a4 ([5]a3) ∧ a1 (a3 U[5,20]a1)

(a) Sensor noise impact on MPRV

  • accuracy. Prediction horizon length is

10 (1s)

10 20 30 40 50 Prediction Step Length (P) 0% 20% 40% 60% 80% 100% Accuracy

a0 a1 a2 a4 [15]a1 ◻[15]a1 ◻[15]a4 ([5]a3) ∧ a1 (a3 U[5,20]a1)

(b) Prediction horizon length impact

  • n MPRV accuracy. Sensor noise

standard deviation is 0.025.

Figure: Impact of sensor noise and prediction horizon length on MPRV accuracy.

a0: absolute value of trajectory error < 0.04m a1: absolute value of trajectory error < 0.08m a2: absolute value of trajectory error < 0.20m a3: absolute speed > 0.6 m/s a4: position > 1.0 m/s

24 / 32

slide-25
SLIDE 25

Evaluation WCET Analysis

Worst Case Execution Time (WCET) Analysis

N.t = tbasic + tloop ∗ N.X ≤ C ∗ N.X (3) where, N.X = ⎧ ⎪ ⎪ ⎨ ⎪ ⎪ ⎩ ∑(N.iSCQ) N is binary operator P + 1 N is unary operator (4) tbasic is the time for ‘Fetch Instruction’ and ‘Increase PC’ etc. in Fig. 3(b) tloop is the time for ’Observer Algorithm’ C is a constant associated with the hardware computation core pipeline. In our design, the execution time is bounded by C = 24e−8(unit: second)2.

2Based on our hardware running at a clock frequency of 100 MHz. 25 / 32

slide-26
SLIDE 26

Evaluation WCET Analysis

20 40 60 80 100 Prediction Step Length (P) 200 400 600 800 ∑N(N.X)

a0 [15]a0 ([15]a3) ∨ a1 ([50]a3) ∨ a1 (a3 U[5,20]a1) ∧ ([20]a4) (a3 U[5,20]a1) U[10,15]a4

Figure: Relationship between N.X and prediction horizon length for MLTL formulas of

varying complexity.

MPRV computational complexity: O(max(S,n ∗ P)), S is the total SCQ memory usage, n is the total number of operators, P is the prediction step length.

26 / 32

slide-27
SLIDE 27

Conclusion

Summary of Work

The primary contribution of this work is providing predictive runtime verificaiton based on system model: extension to an existing state-of-the-art RV tool, R2U2; better mitigation of faults by enabling future-time requirements to be evaluated; hardware realiable by bounding resource usage;

27 / 32

slide-28
SLIDE 28

Conclusion

The End

28 / 32

slide-29
SLIDE 29

Conclusion

References I

Ebru Aydin Gol, Mircea Lazar, and Calin Belta, Temporal logic model predictive control, Automatica 56 (2015), 78–85. Hong Lu and Alessandro Forin, The design and implementation of p2v, an architecture for zero-overhead online verification of software programs, Tech. Report MSR-TR-2007-99, Microsoft Research, August 2007. Gary Nutt, Tutorial: Computer system monitors, Computer 8 (1975),

  • no. 11, 51–61.
  • R. Pellizzoni, P. Meredith, M. Caccamo, and G. Rosu, Hardware

runtime monitoring for dependable cots-based real-time embedded systems, 2008 Real-Time Systems Symposium, Nov 2008,

  • pp. 481–491.

29 / 32

slide-30
SLIDE 30

Conclusion

References II

Vasumathi Raman, Alexandre Donz´ e, Mehdi Maasoumy, Richard M Murray, Alberto Sangiovanni-Vincentelli, and Sanjit A Seshia, Model predictive control with signal temporal logic specifications, Decision and Control (CDC), 2014 IEEE 53rd Annual Conference on, IEEE, 2014, pp. 81–87. Thomas Reinbacher, Kristin Yvonne Rozier, and Johann Schumann, Temporal-logic based runtime observer pairs for system health management of real-time systems, International Conference on Tools and Algorithms for the Construction and Analysis of Systems, Springer, 2014, pp. 357–372.

30 / 32

slide-31
SLIDE 31

Related Work

Hardware Monitor for Temporal Logic

Related Hardware Monitor: 1975 as Nutt [Nut75] proposed using hardware to monitor computer systems. An FPGA-based hardware monitor, called BusMOP [PMCR08]. Hong created an automated tool, called P2V [LF07]. R2U2: soft-coded hardware monitor [RRS14].

31 / 32

slide-32
SLIDE 32

Related Work

Predictive Runtime Verification

Interdisciplinary work between RV and control. Model Predictive Control with Signal Temporal Logic Specifications [RDM+14]. Temporal logic model predictive control [GLB15]

32 / 32